/*==============================================================================
 Copyright (c) 2015-2018 Qualcomm Technologies, Inc.
 All Rights Reserved.
 Confidential and Proprietary - Qualcomm Technologies, Inc.
==============================================================================*/
#ifndef TITAN170_CCI_H
#define TITAN170_CCI_H

/*----------------------------------------------------------------------
        Offset and Mask
----------------------------------------------------------------------*/

#define CCI_REGS_FIRST 0x0 

#define CCI_REGS_LAST 0xc18 

#define CCI_REGS_COUNT 0x52 

#define regCCI_CCI_HW_VERSION 0x0  /*register offset*/
#define CCI_CCI_HW_VERSION_STEP_MASK 0xffff
#define CCI_CCI_HW_VERSION_STEP_SHIFT 0x0
#define CCI_CCI_HW_VERSION_MINOR_VERSION_MASK 0xfff0000
#define CCI_CCI_HW_VERSION_MINOR_VERSION_SHIFT 0x10
#define CCI_CCI_HW_VERSION_MAJOR_VERSION_MASK 0xf0000000
#define CCI_CCI_HW_VERSION_MAJOR_VERSION_SHIFT 0x1c

#define regCCI_CCI_RESET_CMD 0x4  /*register offset*/
#define CCI_CCI_RESET_CMD_STROBED_RST_EN_MASK 0x1
#define CCI_CCI_RESET_CMD_STROBED_RST_EN_SHIFT 0x0
#define CCI_CCI_RESET_CMD_MISC_LOGIC_RST_STB_MASK 0x2
#define CCI_CCI_RESET_CMD_MISC_LOGIC_RST_STB_SHIFT 0x1
#define CCI_CCI_RESET_CMD_SW_REG_RST_STB_MASK 0x4
#define CCI_CCI_RESET_CMD_SW_REG_RST_STB_SHIFT 0x2
#define CCI_CCI_RESET_CMD_UNUSED0_MASK 0x8
#define CCI_CCI_RESET_CMD_UNUSED0_SHIFT 0x3
#define CCI_CCI_RESET_CMD_I2C_M0_RST_STB_MASK 0x10
#define CCI_CCI_RESET_CMD_I2C_M0_RST_STB_SHIFT 0x4
#define CCI_CCI_RESET_CMD_I2C_M0_RD_FIFO_RST_STB_MASK 0x20
#define CCI_CCI_RESET_CMD_I2C_M0_RD_FIFO_RST_STB_SHIFT 0x5
#define CCI_CCI_RESET_CMD_I2C_M0_QCMD_PROC_RST_STB_MASK 0x40
#define CCI_CCI_RESET_CMD_I2C_M0_QCMD_PROC_RST_STB_SHIFT 0x6
#define CCI_CCI_RESET_CMD_I2C_M0_QARB_RST_STB_MASK 0x80
#define CCI_CCI_RESET_CMD_I2C_M0_QARB_RST_STB_SHIFT 0x7
#define CCI_CCI_RESET_CMD_I2C_M0_Q0_RST_STB_MASK 0x100
#define CCI_CCI_RESET_CMD_I2C_M0_Q0_RST_STB_SHIFT 0x8
#define CCI_CCI_RESET_CMD_I2C_M0_Q1_RST_STB_MASK 0x200
#define CCI_CCI_RESET_CMD_I2C_M0_Q1_RST_STB_SHIFT 0x9
#define CCI_CCI_RESET_CMD_UNUSED1_MASK 0xc00
#define CCI_CCI_RESET_CMD_UNUSED1_SHIFT 0xa
#define CCI_CCI_RESET_CMD_I2C_M1_RST_STB_MASK 0x1000
#define CCI_CCI_RESET_CMD_I2C_M1_RST_STB_SHIFT 0xc
#define CCI_CCI_RESET_CMD_I2C_M1_RD_FIFO_RST_STB_MASK 0x2000
#define CCI_CCI_RESET_CMD_I2C_M1_RD_FIFO_RST_STB_SHIFT 0xd
#define CCI_CCI_RESET_CMD_I2C_M1_QCMD_PROC_RST_STB_MASK 0x4000
#define CCI_CCI_RESET_CMD_I2C_M1_QCMD_PROC_RST_STB_SHIFT 0xe
#define CCI_CCI_RESET_CMD_I2C_M1_QARB_RST_STB_MASK 0x8000
#define CCI_CCI_RESET_CMD_I2C_M1_QARB_RST_STB_SHIFT 0xf
#define CCI_CCI_RESET_CMD_I2C_M1_Q0_RST_STB_MASK 0x10000
#define CCI_CCI_RESET_CMD_I2C_M1_Q0_RST_STB_SHIFT 0x10
#define CCI_CCI_RESET_CMD_I2C_M1_Q1_RST_STB_MASK 0x20000
#define CCI_CCI_RESET_CMD_I2C_M1_Q1_RST_STB_SHIFT 0x11
#define CCI_CCI_RESET_CMD_UNUSED2_MASK 0xc0000
#define CCI_CCI_RESET_CMD_UNUSED2_SHIFT 0x12
#define CCI_CCI_RESET_CMD_GPIO_Q0_RST_STB_MASK 0x100000
#define CCI_CCI_RESET_CMD_GPIO_Q0_RST_STB_SHIFT 0x14
#define CCI_CCI_RESET_CMD_GPIO_Q1_RST_STB_MASK 0x200000
#define CCI_CCI_RESET_CMD_GPIO_Q1_RST_STB_SHIFT 0x15
#define CCI_CCI_RESET_CMD_GPIO_Q2_RST_STB_MASK 0x400000
#define CCI_CCI_RESET_CMD_GPIO_Q2_RST_STB_SHIFT 0x16
#define CCI_CCI_RESET_CMD_UNUSED3_MASK 0x800000
#define CCI_CCI_RESET_CMD_UNUSED3_SHIFT 0x17
#define CCI_CCI_RESET_CMD_SYNC_TIMER_0_RST_STB_MASK 0x1000000
#define CCI_CCI_RESET_CMD_SYNC_TIMER_0_RST_STB_SHIFT 0x18
#define CCI_CCI_RESET_CMD_SYNC_TIMER_1_RST_STB_MASK 0x2000000
#define CCI_CCI_RESET_CMD_SYNC_TIMER_1_RST_STB_SHIFT 0x19
#define CCI_CCI_RESET_CMD_SYNC_TIMER_2_RST_STB_MASK 0x4000000
#define CCI_CCI_RESET_CMD_SYNC_TIMER_2_RST_STB_SHIFT 0x1a
#define CCI_CCI_RESET_CMD_SYNC_TIMER_3_RST_STB_MASK 0x8000000
#define CCI_CCI_RESET_CMD_SYNC_TIMER_3_RST_STB_SHIFT 0x1b
#define CCI_CCI_RESET_CMD_UNUSED4_MASK 0x30000000
#define CCI_CCI_RESET_CMD_UNUSED4_SHIFT 0x1c
#define CCI_CCI_RESET_CMD_CCI_CLK_DOMAIN_RST_MASK 0x40000000
#define CCI_CCI_RESET_CMD_CCI_CLK_DOMAIN_RST_SHIFT 0x1e
#define CCI_CCI_RESET_CMD_AHB_CLK_DOMAIN_RST_MASK 0x80000000
#define CCI_CCI_RESET_CMD_AHB_CLK_DOMAIN_RST_SHIFT 0x1f

#define regCCI_CCI_QUEUE_START 0x8  /*register offset*/
#define CCI_CCI_QUEUE_START_I2C_M0_Q0_START_MASK 0x1
#define CCI_CCI_QUEUE_START_I2C_M0_Q0_START_SHIFT 0x0
#define CCI_CCI_QUEUE_START_I2C_M0_Q1_START_MASK 0x2
#define CCI_CCI_QUEUE_START_I2C_M0_Q1_START_SHIFT 0x1
#define CCI_CCI_QUEUE_START_I2C_M1_Q0_START_MASK 0x4
#define CCI_CCI_QUEUE_START_I2C_M1_Q0_START_SHIFT 0x2
#define CCI_CCI_QUEUE_START_I2C_M1_Q1_START_MASK 0x8
#define CCI_CCI_QUEUE_START_I2C_M1_Q1_START_SHIFT 0x3
#define CCI_CCI_QUEUE_START_GPIO_Q0_START_MASK 0x10
#define CCI_CCI_QUEUE_START_GPIO_Q0_START_SHIFT 0x4
#define CCI_CCI_QUEUE_START_GPIO_Q1_START_MASK 0x20
#define CCI_CCI_QUEUE_START_GPIO_Q1_START_SHIFT 0x5
#define CCI_CCI_QUEUE_START_GPIO_Q2_START_MASK 0x40
#define CCI_CCI_QUEUE_START_GPIO_Q2_START_SHIFT 0x6
#define CCI_CCI_QUEUE_START_UNUSED0_MASK 0xffffff80
#define CCI_CCI_QUEUE_START_UNUSED0_SHIFT 0x7

#define regCCI_CCI_TESTBUS_SEL 0xc  /*register offset*/
#define CCI_CCI_TESTBUS_SEL_TESTBUS_EN_MASK 0x1
#define CCI_CCI_TESTBUS_SEL_TESTBUS_EN_SHIFT 0x0
#define CCI_CCI_TESTBUS_SEL_UNUSED0_MASK 0xe
#define CCI_CCI_TESTBUS_SEL_UNUSED0_SHIFT 0x1
#define CCI_CCI_TESTBUS_SEL_TESTBUS_SEL_MASK 0xffffff0
#define CCI_CCI_TESTBUS_SEL_TESTBUS_SEL_SHIFT 0x4
#define CCI_CCI_TESTBUS_SEL_DOMAIN_SEL_MASK 0x10000000
#define CCI_CCI_TESTBUS_SEL_DOMAIN_SEL_SHIFT 0x1c
#define CCI_CCI_TESTBUS_SEL_UNUSED1_MASK 0xe0000000
#define CCI_CCI_TESTBUS_SEL_UNUSED1_SHIFT 0x1d

#define regCCI_CCI_SET_CID_SYNC_TIMER_0 0x10  /*register offset*/
#define CCI_CCI_SET_CID_SYNC_TIMER_0_SENSOR_SYNC_CID_MASK 0x7f
#define CCI_CCI_SET_CID_SYNC_TIMER_0_SENSOR_SYNC_CID_SHIFT 0x0
#define CCI_CCI_SET_CID_SYNC_TIMER_0_UNUSED0_MASK 0xffffff80
#define CCI_CCI_SET_CID_SYNC_TIMER_0_UNUSED0_SHIFT 0x7

#define regCCI_CCI_SET_CID_SYNC_TIMER_1 0x14  /*register offset*/
#define CCI_CCI_SET_CID_SYNC_TIMER_1_SENSOR_SYNC_CID_MASK 0x7f
#define CCI_CCI_SET_CID_SYNC_TIMER_1_SENSOR_SYNC_CID_SHIFT 0x0
#define CCI_CCI_SET_CID_SYNC_TIMER_1_UNUSED0_MASK 0xffffff80
#define CCI_CCI_SET_CID_SYNC_TIMER_1_UNUSED0_SHIFT 0x7

#define regCCI_CCI_SET_CID_SYNC_TIMER_2 0x18  /*register offset*/
#define CCI_CCI_SET_CID_SYNC_TIMER_2_SENSOR_SYNC_CID_MASK 0x7f
#define CCI_CCI_SET_CID_SYNC_TIMER_2_SENSOR_SYNC_CID_SHIFT 0x0
#define CCI_CCI_SET_CID_SYNC_TIMER_2_UNUSED0_MASK 0xffffff80
#define CCI_CCI_SET_CID_SYNC_TIMER_2_UNUSED0_SHIFT 0x7

#define regCCI_CCI_SET_CID_SYNC_TIMER_3 0x1c  /*register offset*/
#define CCI_CCI_SET_CID_SYNC_TIMER_3_SENSOR_SYNC_CID_MASK 0x7f
#define CCI_CCI_SET_CID_SYNC_TIMER_3_SENSOR_SYNC_CID_SHIFT 0x0
#define CCI_CCI_SET_CID_SYNC_TIMER_3_UNUSED0_MASK 0xffffff80
#define CCI_CCI_SET_CID_SYNC_TIMER_3_UNUSED0_SHIFT 0x7

#define regCCI_CCI_GPIO_STATUS 0x30  /*register offset*/
#define CCI_CCI_GPIO_STATUS_GPIO_IN0_MASK 0x1
#define CCI_CCI_GPIO_STATUS_GPIO_IN0_SHIFT 0x0
#define CCI_CCI_GPIO_STATUS_GPIO_IN1_MASK 0x2
#define CCI_CCI_GPIO_STATUS_GPIO_IN1_SHIFT 0x1
#define CCI_CCI_GPIO_STATUS_GPIO_IN2_MASK 0x4
#define CCI_CCI_GPIO_STATUS_GPIO_IN2_SHIFT 0x2
#define CCI_CCI_GPIO_STATUS_UNUSED0_MASK 0xf8
#define CCI_CCI_GPIO_STATUS_UNUSED0_SHIFT 0x3
#define CCI_CCI_GPIO_STATUS_GPIO_OUT0_MASK 0x100
#define CCI_CCI_GPIO_STATUS_GPIO_OUT0_SHIFT 0x8
#define CCI_CCI_GPIO_STATUS_GPIO_OUT1_MASK 0x200
#define CCI_CCI_GPIO_STATUS_GPIO_OUT1_SHIFT 0x9
#define CCI_CCI_GPIO_STATUS_GPIO_OUT2_MASK 0x400
#define CCI_CCI_GPIO_STATUS_GPIO_OUT2_SHIFT 0xa
#define CCI_CCI_GPIO_STATUS_GPIO_OUT3_MASK 0x800
#define CCI_CCI_GPIO_STATUS_GPIO_OUT3_SHIFT 0xb
#define CCI_CCI_GPIO_STATUS_GPIO_OUT4_MASK 0x1000
#define CCI_CCI_GPIO_STATUS_GPIO_OUT4_SHIFT 0xc
#define CCI_CCI_GPIO_STATUS_UNUSED1_MASK 0xffffe000
#define CCI_CCI_GPIO_STATUS_UNUSED1_SHIFT 0xd

#define regCCI_CCI_HALT_REQ 0x34  /*register offset*/
#define CCI_CCI_HALT_REQ_I2C_M0_Q0Q1_HALT_REQ_MASK 0x1
#define CCI_CCI_HALT_REQ_I2C_M0_Q0Q1_HALT_REQ_SHIFT 0x0
#define CCI_CCI_HALT_REQ_I2C_M1_Q0Q1_HALT_REQ_MASK 0x2
#define CCI_CCI_HALT_REQ_I2C_M1_Q0Q1_HALT_REQ_SHIFT 0x1
#define CCI_CCI_HALT_REQ_UNUSED0_MASK 0xfffffffc
#define CCI_CCI_HALT_REQ_UNUSED0_SHIFT 0x2

#define regCCI_CCI_CLK_DISABLE 0x38  /*register offset*/
#define CCI_CCI_CLK_DISABLE_I2C_M0_CLK_DISABLE_MASK 0x1
#define CCI_CCI_CLK_DISABLE_I2C_M0_CLK_DISABLE_SHIFT 0x0
#define CCI_CCI_CLK_DISABLE_I2C_M1_CLK_DISABLE_MASK 0x2
#define CCI_CCI_CLK_DISABLE_I2C_M1_CLK_DISABLE_SHIFT 0x1
#define CCI_CCI_CLK_DISABLE_GPIO_0_CLK_DISABLE_MASK 0x4
#define CCI_CCI_CLK_DISABLE_GPIO_0_CLK_DISABLE_SHIFT 0x2
#define CCI_CCI_CLK_DISABLE_GPIO_1_CLK_DISABLE_MASK 0x8
#define CCI_CCI_CLK_DISABLE_GPIO_1_CLK_DISABLE_SHIFT 0x3
#define CCI_CCI_CLK_DISABLE_GPIO_2_CLK_DISABLE_MASK 0x10
#define CCI_CCI_CLK_DISABLE_GPIO_2_CLK_DISABLE_SHIFT 0x4
#define CCI_CCI_CLK_DISABLE_UNUSED0_MASK 0xffffffe0
#define CCI_CCI_CLK_DISABLE_UNUSED0_SHIFT 0x5

#define regCCI_CCI_I2C_M0_SCL_CTL 0x100  /*register offset*/
#define CCI_CCI_I2C_M0_SCL_CTL_HW_TLOW_MASK 0xfff
#define CCI_CCI_I2C_M0_SCL_CTL_HW_TLOW_SHIFT 0x0
#define CCI_CCI_I2C_M0_SCL_CTL_UNUSED0_MASK 0xf000
#define CCI_CCI_I2C_M0_SCL_CTL_UNUSED0_SHIFT 0xc
#define CCI_CCI_I2C_M0_SCL_CTL_HW_THIGH_MASK 0xfff0000
#define CCI_CCI_I2C_M0_SCL_CTL_HW_THIGH_SHIFT 0x10
#define CCI_CCI_I2C_M0_SCL_CTL_UNUSED1_MASK 0xf0000000
#define CCI_CCI_I2C_M0_SCL_CTL_UNUSED1_SHIFT 0x1c

#define regCCI_CCI_I2C_M0_SDA_CTL_0 0x104  /*register offset*/
#define CCI_CCI_I2C_M0_SDA_CTL_0_HW_TSU_STA_MASK 0xff
#define CCI_CCI_I2C_M0_SDA_CTL_0_HW_TSU_STA_SHIFT 0x0
#define CCI_CCI_I2C_M0_SDA_CTL_0_UNUSED0_MASK 0xff00
#define CCI_CCI_I2C_M0_SDA_CTL_0_UNUSED0_SHIFT 0x8
#define CCI_CCI_I2C_M0_SDA_CTL_0_HW_TSU_STO_MASK 0xff0000
#define CCI_CCI_I2C_M0_SDA_CTL_0_HW_TSU_STO_SHIFT 0x10
#define CCI_CCI_I2C_M0_SDA_CTL_0_UNUSED1_MASK 0xff000000
#define CCI_CCI_I2C_M0_SDA_CTL_0_UNUSED1_SHIFT 0x18

#define regCCI_CCI_I2C_M0_SDA_CTL_1 0x108  /*register offset*/
#define CCI_CCI_I2C_M0_SDA_CTL_1_HW_THD_STA_MASK 0xff
#define CCI_CCI_I2C_M0_SDA_CTL_1_HW_THD_STA_SHIFT 0x0
#define CCI_CCI_I2C_M0_SDA_CTL_1_UNUSED0_MASK 0xff00
#define CCI_CCI_I2C_M0_SDA_CTL_1_UNUSED0_SHIFT 0x8
#define CCI_CCI_I2C_M0_SDA_CTL_1_HW_THD_DAT_MASK 0xff0000
#define CCI_CCI_I2C_M0_SDA_CTL_1_HW_THD_DAT_SHIFT 0x10
#define CCI_CCI_I2C_M0_SDA_CTL_1_UNUSED1_MASK 0xff000000
#define CCI_CCI_I2C_M0_SDA_CTL_1_UNUSED1_SHIFT 0x18

#define regCCI_CCI_I2C_M0_SDA_CTL_2 0x10c  /*register offset*/
#define CCI_CCI_I2C_M0_SDA_CTL_2_HW_TBUF_MASK 0xfff
#define CCI_CCI_I2C_M0_SDA_CTL_2_HW_TBUF_SHIFT 0x0
#define CCI_CCI_I2C_M0_SDA_CTL_2_UNUSED0_MASK 0xfffff000
#define CCI_CCI_I2C_M0_SDA_CTL_2_UNUSED0_SHIFT 0xc

#define regCCI_CCI_I2C_M0_MISC_CTL 0x110  /*register offset*/
#define CCI_CCI_I2C_M0_MISC_CTL_HW_TSP_MASK 0x3
#define CCI_CCI_I2C_M0_MISC_CTL_HW_TSP_SHIFT 0x0
#define CCI_CCI_I2C_M0_MISC_CTL_UNUSED0_MASK 0xc
#define CCI_CCI_I2C_M0_MISC_CTL_UNUSED0_SHIFT 0x2
#define CCI_CCI_I2C_M0_MISC_CTL_HW_TRDHLD_MASK 0x70
#define CCI_CCI_I2C_M0_MISC_CTL_HW_TRDHLD_SHIFT 0x4
#define CCI_CCI_I2C_M0_MISC_CTL_UNUSED1_MASK 0x80
#define CCI_CCI_I2C_M0_MISC_CTL_UNUSED1_SHIFT 0x7
#define CCI_CCI_I2C_M0_MISC_CTL_HW_SCL_STRETCH_EN_MASK 0x100
#define CCI_CCI_I2C_M0_MISC_CTL_HW_SCL_STRETCH_EN_SHIFT 0x8
#define CCI_CCI_I2C_M0_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_MASK 0x200
#define CCI_CCI_I2C_M0_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_SHIFT 0x9
#define CCI_CCI_I2C_M0_MISC_CTL_UNUSED2_MASK 0xfffffc00
#define CCI_CCI_I2C_M0_MISC_CTL_UNUSED2_SHIFT 0xa

#define regCCI_CCI_I2C_M0_STATUS 0x114  /*register offset*/
#define CCI_CCI_I2C_M0_STATUS_BIT_FSM_STATE_MASK 0x7ff
#define CCI_CCI_I2C_M0_STATUS_BIT_FSM_STATE_SHIFT 0x0
#define CCI_CCI_I2C_M0_STATUS_UNUSED0_MASK 0x800
#define CCI_CCI_I2C_M0_STATUS_UNUSED0_SHIFT 0xb
#define CCI_CCI_I2C_M0_STATUS_SDA_OUT_MASK 0x1000
#define CCI_CCI_I2C_M0_STATUS_SDA_OUT_SHIFT 0xc
#define CCI_CCI_I2C_M0_STATUS_SCL_OUT_MASK 0x2000
#define CCI_CCI_I2C_M0_STATUS_SCL_OUT_SHIFT 0xd
#define CCI_CCI_I2C_M0_STATUS_SDA_IN_MASK 0x4000
#define CCI_CCI_I2C_M0_STATUS_SDA_IN_SHIFT 0xe
#define CCI_CCI_I2C_M0_STATUS_SCL_IN_MASK 0x8000
#define CCI_CCI_I2C_M0_STATUS_SCL_IN_SHIFT 0xf
#define CCI_CCI_I2C_M0_STATUS_WORD_FSM_STATE_MASK 0x7f0000
#define CCI_CCI_I2C_M0_STATUS_WORD_FSM_STATE_SHIFT 0x10
#define CCI_CCI_I2C_M0_STATUS_ACK_FSM_STATE_MASK 0x3800000
#define CCI_CCI_I2C_M0_STATUS_ACK_FSM_STATE_SHIFT 0x17
#define CCI_CCI_I2C_M0_STATUS_UNUSED1_MASK 0xc000000
#define CCI_CCI_I2C_M0_STATUS_UNUSED1_SHIFT 0x1a
#define CCI_CCI_I2C_M0_STATUS_CMD_FSM_STATE_MASK 0xf0000000
#define CCI_CCI_I2C_M0_STATUS_CMD_FSM_STATE_SHIFT 0x1c

#define regCCI_CCI_I2C_M0_READ_DATA 0x118  /*register offset*/
#define CCI_CCI_I2C_M0_READ_DATA_READ_DATA_MASK 0xffffffff
#define CCI_CCI_I2C_M0_READ_DATA_READ_DATA_SHIFT 0x0

#define regCCI_CCI_I2C_M0_READ_BUF_LEVEL 0x11c  /*register offset*/
#define CCI_CCI_I2C_M0_READ_BUF_LEVEL_READ_BUF_LEVEL_MASK 0x7f
#define CCI_CCI_I2C_M0_READ_BUF_LEVEL_READ_BUF_LEVEL_SHIFT 0x0
#define CCI_CCI_I2C_M0_READ_BUF_LEVEL_UNUSED0_MASK 0xffffff80
#define CCI_CCI_I2C_M0_READ_BUF_LEVEL_UNUSED0_SHIFT 0x7

#define regCCI_CCI_I2C_M0_RD_THRESHOLD 0x120  /*register offset*/
#define CCI_CCI_I2C_M0_RD_THRESHOLD_THRESHOLD_MASK 0x7f
#define CCI_CCI_I2C_M0_RD_THRESHOLD_THRESHOLD_SHIFT 0x0
#define CCI_CCI_I2C_M0_RD_THRESHOLD_UNUSED0_MASK 0xffffff80
#define CCI_CCI_I2C_M0_RD_THRESHOLD_UNUSED0_SHIFT 0x7

#define regCCI_CCI_I2C_M1_SCL_CTL 0x200  /*register offset*/
#define CCI_CCI_I2C_M1_SCL_CTL_HW_TLOW_MASK 0xfff
#define CCI_CCI_I2C_M1_SCL_CTL_HW_TLOW_SHIFT 0x0
#define CCI_CCI_I2C_M1_SCL_CTL_UNUSED0_MASK 0xf000
#define CCI_CCI_I2C_M1_SCL_CTL_UNUSED0_SHIFT 0xc
#define CCI_CCI_I2C_M1_SCL_CTL_HW_THIGH_MASK 0xfff0000
#define CCI_CCI_I2C_M1_SCL_CTL_HW_THIGH_SHIFT 0x10
#define CCI_CCI_I2C_M1_SCL_CTL_UNUSED1_MASK 0xf0000000
#define CCI_CCI_I2C_M1_SCL_CTL_UNUSED1_SHIFT 0x1c

#define regCCI_CCI_I2C_M1_SDA_CTL_0 0x204  /*register offset*/
#define CCI_CCI_I2C_M1_SDA_CTL_0_HW_TSU_STA_MASK 0xff
#define CCI_CCI_I2C_M1_SDA_CTL_0_HW_TSU_STA_SHIFT 0x0
#define CCI_CCI_I2C_M1_SDA_CTL_0_UNUSED0_MASK 0xff00
#define CCI_CCI_I2C_M1_SDA_CTL_0_UNUSED0_SHIFT 0x8
#define CCI_CCI_I2C_M1_SDA_CTL_0_HW_TSU_STO_MASK 0xff0000
#define CCI_CCI_I2C_M1_SDA_CTL_0_HW_TSU_STO_SHIFT 0x10
#define CCI_CCI_I2C_M1_SDA_CTL_0_UNUSED1_MASK 0xff000000
#define CCI_CCI_I2C_M1_SDA_CTL_0_UNUSED1_SHIFT 0x18

#define regCCI_CCI_I2C_M1_SDA_CTL_1 0x208  /*register offset*/
#define CCI_CCI_I2C_M1_SDA_CTL_1_HW_THD_STA_MASK 0xff
#define CCI_CCI_I2C_M1_SDA_CTL_1_HW_THD_STA_SHIFT 0x0
#define CCI_CCI_I2C_M1_SDA_CTL_1_UNUSED0_MASK 0xff00
#define CCI_CCI_I2C_M1_SDA_CTL_1_UNUSED0_SHIFT 0x8
#define CCI_CCI_I2C_M1_SDA_CTL_1_HW_THD_DAT_MASK 0xff0000
#define CCI_CCI_I2C_M1_SDA_CTL_1_HW_THD_DAT_SHIFT 0x10
#define CCI_CCI_I2C_M1_SDA_CTL_1_UNUSED1_MASK 0xff000000
#define CCI_CCI_I2C_M1_SDA_CTL_1_UNUSED1_SHIFT 0x18

#define regCCI_CCI_I2C_M1_SDA_CTL_2 0x20c  /*register offset*/
#define CCI_CCI_I2C_M1_SDA_CTL_2_HW_TBUF_MASK 0xfff
#define CCI_CCI_I2C_M1_SDA_CTL_2_HW_TBUF_SHIFT 0x0
#define CCI_CCI_I2C_M1_SDA_CTL_2_UNUSED0_MASK 0xfffff000
#define CCI_CCI_I2C_M1_SDA_CTL_2_UNUSED0_SHIFT 0xc

#define regCCI_CCI_I2C_M1_MISC_CTL 0x210  /*register offset*/
#define CCI_CCI_I2C_M1_MISC_CTL_HW_TSP_MASK 0x3
#define CCI_CCI_I2C_M1_MISC_CTL_HW_TSP_SHIFT 0x0
#define CCI_CCI_I2C_M1_MISC_CTL_UNUSED0_MASK 0xc
#define CCI_CCI_I2C_M1_MISC_CTL_UNUSED0_SHIFT 0x2
#define CCI_CCI_I2C_M1_MISC_CTL_HW_TRDHLD_MASK 0x70
#define CCI_CCI_I2C_M1_MISC_CTL_HW_TRDHLD_SHIFT 0x4
#define CCI_CCI_I2C_M1_MISC_CTL_UNUSED1_MASK 0x80
#define CCI_CCI_I2C_M1_MISC_CTL_UNUSED1_SHIFT 0x7
#define CCI_CCI_I2C_M1_MISC_CTL_HW_SCL_STRETCH_EN_MASK 0x100
#define CCI_CCI_I2C_M1_MISC_CTL_HW_SCL_STRETCH_EN_SHIFT 0x8
#define CCI_CCI_I2C_M1_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_MASK 0x200
#define CCI_CCI_I2C_M1_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_SHIFT 0x9
#define CCI_CCI_I2C_M1_MISC_CTL_UNUSED2_MASK 0xfffffc00
#define CCI_CCI_I2C_M1_MISC_CTL_UNUSED2_SHIFT 0xa

#define regCCI_CCI_I2C_M1_STATUS 0x214  /*register offset*/
#define CCI_CCI_I2C_M1_STATUS_BIT_FSM_STATE_MASK 0x7ff
#define CCI_CCI_I2C_M1_STATUS_BIT_FSM_STATE_SHIFT 0x0
#define CCI_CCI_I2C_M1_STATUS_UNUSED0_MASK 0x800
#define CCI_CCI_I2C_M1_STATUS_UNUSED0_SHIFT 0xb
#define CCI_CCI_I2C_M1_STATUS_SDA_OUT_MASK 0x1000
#define CCI_CCI_I2C_M1_STATUS_SDA_OUT_SHIFT 0xc
#define CCI_CCI_I2C_M1_STATUS_SCL_OUT_MASK 0x2000
#define CCI_CCI_I2C_M1_STATUS_SCL_OUT_SHIFT 0xd
#define CCI_CCI_I2C_M1_STATUS_SDA_IN_MASK 0x4000
#define CCI_CCI_I2C_M1_STATUS_SDA_IN_SHIFT 0xe
#define CCI_CCI_I2C_M1_STATUS_SCL_IN_MASK 0x8000
#define CCI_CCI_I2C_M1_STATUS_SCL_IN_SHIFT 0xf
#define CCI_CCI_I2C_M1_STATUS_WORD_FSM_STATE_MASK 0x7f0000
#define CCI_CCI_I2C_M1_STATUS_WORD_FSM_STATE_SHIFT 0x10
#define CCI_CCI_I2C_M1_STATUS_ACK_FSM_STATE_MASK 0x3800000
#define CCI_CCI_I2C_M1_STATUS_ACK_FSM_STATE_SHIFT 0x17
#define CCI_CCI_I2C_M1_STATUS_UNUSED1_MASK 0xc000000
#define CCI_CCI_I2C_M1_STATUS_UNUSED1_SHIFT 0x1a
#define CCI_CCI_I2C_M1_STATUS_CMD_FSM_STATE_MASK 0xf0000000
#define CCI_CCI_I2C_M1_STATUS_CMD_FSM_STATE_SHIFT 0x1c

#define regCCI_CCI_I2C_M1_READ_DATA 0x218  /*register offset*/
#define CCI_CCI_I2C_M1_READ_DATA_READ_DATA_MASK 0xffffffff
#define CCI_CCI_I2C_M1_READ_DATA_READ_DATA_SHIFT 0x0

#define regCCI_CCI_I2C_M1_READ_BUF_LEVEL 0x21c  /*register offset*/
#define CCI_CCI_I2C_M1_READ_BUF_LEVEL_READ_BUF_LEVEL_MASK 0x7f
#define CCI_CCI_I2C_M1_READ_BUF_LEVEL_READ_BUF_LEVEL_SHIFT 0x0
#define CCI_CCI_I2C_M1_READ_BUF_LEVEL_UNUSED0_MASK 0xffffff80
#define CCI_CCI_I2C_M1_READ_BUF_LEVEL_UNUSED0_SHIFT 0x7

#define regCCI_CCI_I2C_M1_RD_THRESHOLD 0x220  /*register offset*/
#define CCI_CCI_I2C_M1_RD_THRESHOLD_THRESHOLD_MASK 0x7f
#define CCI_CCI_I2C_M1_RD_THRESHOLD_THRESHOLD_SHIFT 0x0
#define CCI_CCI_I2C_M1_RD_THRESHOLD_UNUSED0_MASK 0xffffff80
#define CCI_CCI_I2C_M1_RD_THRESHOLD_UNUSED0_SHIFT 0x7

#define regCCI_CCI_I2C_M0_Q0_EXEC_WORD_CNT 0x300  /*register offset*/
#define CCI_CCI_I2C_M0_Q0_EXEC_WORD_CNT_EXEC_WORD_CNT_MASK 0xff
#define CCI_CCI_I2C_M0_Q0_EXEC_WORD_CNT_EXEC_WORD_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q0_EXEC_WORD_CNT_UNUSED0_MASK 0xffffff00
#define CCI_CCI_I2C_M0_Q0_EXEC_WORD_CNT_UNUSED0_SHIFT 0x8

#define regCCI_CCI_I2C_M0_Q0_CUR_WORD_CNT 0x304  /*register offset*/
#define CCI_CCI_I2C_M0_Q0_CUR_WORD_CNT_CUR_WORD_CNT_MASK 0xff
#define CCI_CCI_I2C_M0_Q0_CUR_WORD_CNT_CUR_WORD_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q0_CUR_WORD_CNT_UNUSED0_MASK 0xffffff00
#define CCI_CCI_I2C_M0_Q0_CUR_WORD_CNT_UNUSED0_SHIFT 0x8

#define regCCI_CCI_I2C_M0_Q0_CUR_CMD 0x308  /*register offset*/
#define CCI_CCI_I2C_M0_Q0_CUR_CMD_CUR_CMD_MASK 0xffffffff
#define CCI_CCI_I2C_M0_Q0_CUR_CMD_CUR_CMD_SHIFT 0x0

#define regCCI_CCI_I2C_M0_Q0_REPORT_STATUS 0x30c  /*register offset*/
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_LINE_CNT_MASK 0x3fff
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_LINE_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_UNUSED0_MASK 0xc000
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_UNUSED0_SHIFT 0xe
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_FRAME_CNT_MASK 0xff0000
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_FRAME_CNT_SHIFT 0x10
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_CID_MASK 0xf000000
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_CID_SHIFT 0x18
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_REPORT_ID_MASK 0xf0000000
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_REPORT_ID_SHIFT 0x1c

#define regCCI_CCI_I2C_M0_Q0_LOAD_DATA 0x310  /*register offset*/
#define CCI_CCI_I2C_M0_Q0_LOAD_DATA_LOAD_DATA_MASK 0xffffffff
#define CCI_CCI_I2C_M0_Q0_LOAD_DATA_LOAD_DATA_SHIFT 0x0

#define regCCI_CCI_I2C_M0_Q0_DEBUG_INFO 0x314  /*register offset*/
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_SLAVE_ID_MASK 0x7f
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_SLAVE_ID_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_UNUSED0_MASK 0xf80
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_UNUSED0_SHIFT 0x7
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_RETRY_CNT_MASK 0x3000
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_RETRY_CNT_SHIFT 0xc
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_CSI_SENSOR_SYNC_ID_MASK 0xc000
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_CSI_SENSOR_SYNC_ID_SHIFT 0xe
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_UNUSED1_MASK 0xffff0000
#define CCI_CCI_I2C_M0_Q0_DEBUG_INFO_UNUSED1_SHIFT 0x10

#define regCCI_CCI_I2C_M0_Q0_REPORT_STATUS_1 0x318  /*register offset*/
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_1_CID_MASK 0x7f
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_1_CID_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_1_UNUSED0_MASK 0xffffff80
#define CCI_CCI_I2C_M0_Q0_REPORT_STATUS_1_UNUSED0_SHIFT 0x7

#define regCCI_CCI_I2C_M0_Q1_EXEC_WORD_CNT 0x400  /*register offset*/
#define CCI_CCI_I2C_M0_Q1_EXEC_WORD_CNT_EXEC_WORD_CNT_MASK 0x3f
#define CCI_CCI_I2C_M0_Q1_EXEC_WORD_CNT_EXEC_WORD_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q1_EXEC_WORD_CNT_UNUSED0_MASK 0xffffffc0
#define CCI_CCI_I2C_M0_Q1_EXEC_WORD_CNT_UNUSED0_SHIFT 0x6

#define regCCI_CCI_I2C_M0_Q1_CUR_WORD_CNT 0x404  /*register offset*/
#define CCI_CCI_I2C_M0_Q1_CUR_WORD_CNT_CUR_WORD_CNT_MASK 0x3f
#define CCI_CCI_I2C_M0_Q1_CUR_WORD_CNT_CUR_WORD_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q1_CUR_WORD_CNT_UNUSED0_MASK 0xffffffc0
#define CCI_CCI_I2C_M0_Q1_CUR_WORD_CNT_UNUSED0_SHIFT 0x6

#define regCCI_CCI_I2C_M0_Q1_CUR_CMD 0x408  /*register offset*/
#define CCI_CCI_I2C_M0_Q1_CUR_CMD_CUR_CMD_MASK 0xffffffff
#define CCI_CCI_I2C_M0_Q1_CUR_CMD_CUR_CMD_SHIFT 0x0

#define regCCI_CCI_I2C_M0_Q1_REPORT_STATUS 0x40c  /*register offset*/
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_LINE_CNT_MASK 0x3fff
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_LINE_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_UNUSED0_MASK 0xc000
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_UNUSED0_SHIFT 0xe
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_FRAME_CNT_MASK 0xff0000
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_FRAME_CNT_SHIFT 0x10
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_CID_MASK 0xf000000
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_CID_SHIFT 0x18
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_REPORT_ID_MASK 0xf0000000
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_REPORT_ID_SHIFT 0x1c

#define regCCI_CCI_I2C_M0_Q1_LOAD_DATA 0x410  /*register offset*/
#define CCI_CCI_I2C_M0_Q1_LOAD_DATA_LOAD_DATA_MASK 0xffffffff
#define CCI_CCI_I2C_M0_Q1_LOAD_DATA_LOAD_DATA_SHIFT 0x0

#define regCCI_CCI_I2C_M0_Q1_DEBUG_INFO 0x414  /*register offset*/
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_SLAVE_ID_MASK 0x7f
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_SLAVE_ID_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_UNUSED0_MASK 0xf80
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_UNUSED0_SHIFT 0x7
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_RETRY_CNT_MASK 0x3000
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_RETRY_CNT_SHIFT 0xc
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_CSI_SENSOR_SYNC_ID_MASK 0xc000
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_CSI_SENSOR_SYNC_ID_SHIFT 0xe
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_UNUSED1_MASK 0xffff0000
#define CCI_CCI_I2C_M0_Q1_DEBUG_INFO_UNUSED1_SHIFT 0x10

#define regCCI_CCI_I2C_M0_Q1_REPORT_STATUS_1 0x418  /*register offset*/
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_1_CID_MASK 0x7f
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_1_CID_SHIFT 0x0
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_1_UNUSED0_MASK 0xffffff80
#define CCI_CCI_I2C_M0_Q1_REPORT_STATUS_1_UNUSED0_SHIFT 0x7

#define regCCI_CCI_I2C_M1_Q0_EXEC_WORD_CNT 0x500  /*register offset*/
#define CCI_CCI_I2C_M1_Q0_EXEC_WORD_CNT_EXEC_WORD_CNT_MASK 0xff
#define CCI_CCI_I2C_M1_Q0_EXEC_WORD_CNT_EXEC_WORD_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q0_EXEC_WORD_CNT_UNUSED0_MASK 0xffffff00
#define CCI_CCI_I2C_M1_Q0_EXEC_WORD_CNT_UNUSED0_SHIFT 0x8

#define regCCI_CCI_I2C_M1_Q0_CUR_WORD_CNT 0x504  /*register offset*/
#define CCI_CCI_I2C_M1_Q0_CUR_WORD_CNT_CUR_WORD_CNT_MASK 0xff
#define CCI_CCI_I2C_M1_Q0_CUR_WORD_CNT_CUR_WORD_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q0_CUR_WORD_CNT_UNUSED0_MASK 0xffffff00
#define CCI_CCI_I2C_M1_Q0_CUR_WORD_CNT_UNUSED0_SHIFT 0x8

#define regCCI_CCI_I2C_M1_Q0_CUR_CMD 0x508  /*register offset*/
#define CCI_CCI_I2C_M1_Q0_CUR_CMD_CUR_CMD_MASK 0xffffffff
#define CCI_CCI_I2C_M1_Q0_CUR_CMD_CUR_CMD_SHIFT 0x0

#define regCCI_CCI_I2C_M1_Q0_REPORT_STATUS 0x50c  /*register offset*/
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_LINE_CNT_MASK 0x3fff
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_LINE_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_UNUSED0_MASK 0xc000
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_UNUSED0_SHIFT 0xe
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_FRAME_CNT_MASK 0xff0000
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_FRAME_CNT_SHIFT 0x10
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_CID_MASK 0xf000000
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_CID_SHIFT 0x18
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_REPORT_ID_MASK 0xf0000000
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_REPORT_ID_SHIFT 0x1c

#define regCCI_CCI_I2C_M1_Q0_LOAD_DATA 0x510  /*register offset*/
#define CCI_CCI_I2C_M1_Q0_LOAD_DATA_LOAD_DATA_MASK 0xffffffff
#define CCI_CCI_I2C_M1_Q0_LOAD_DATA_LOAD_DATA_SHIFT 0x0

#define regCCI_CCI_I2C_M1_Q0_DEBUG_INFO 0x514  /*register offset*/
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_SLAVE_ID_MASK 0x7f
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_SLAVE_ID_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_UNUSED0_MASK 0xf80
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_UNUSED0_SHIFT 0x7
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_RETRY_CNT_MASK 0x3000
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_RETRY_CNT_SHIFT 0xc
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_CSI_SENSOR_SYNC_ID_MASK 0xc000
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_CSI_SENSOR_SYNC_ID_SHIFT 0xe
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_UNUSED1_MASK 0xffff0000
#define CCI_CCI_I2C_M1_Q0_DEBUG_INFO_UNUSED1_SHIFT 0x10

#define regCCI_CCI_I2C_M1_Q0_REPORT_STATUS_1 0x518  /*register offset*/
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_1_CID_MASK 0x7f
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_1_CID_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_1_UNUSED0_MASK 0xffffff80
#define CCI_CCI_I2C_M1_Q0_REPORT_STATUS_1_UNUSED0_SHIFT 0x7

#define regCCI_CCI_I2C_M1_Q1_EXEC_WORD_CNT 0x600  /*register offset*/
#define CCI_CCI_I2C_M1_Q1_EXEC_WORD_CNT_EXEC_WORD_CNT_MASK 0x3f
#define CCI_CCI_I2C_M1_Q1_EXEC_WORD_CNT_EXEC_WORD_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q1_EXEC_WORD_CNT_UNUSED0_MASK 0xffffffc0
#define CCI_CCI_I2C_M1_Q1_EXEC_WORD_CNT_UNUSED0_SHIFT 0x6

#define regCCI_CCI_I2C_M1_Q1_CUR_WORD_CNT 0x604  /*register offset*/
#define CCI_CCI_I2C_M1_Q1_CUR_WORD_CNT_CUR_WORD_CNT_MASK 0x3f
#define CCI_CCI_I2C_M1_Q1_CUR_WORD_CNT_CUR_WORD_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q1_CUR_WORD_CNT_UNUSED0_MASK 0xffffffc0
#define CCI_CCI_I2C_M1_Q1_CUR_WORD_CNT_UNUSED0_SHIFT 0x6

#define regCCI_CCI_I2C_M1_Q1_CUR_CMD 0x608  /*register offset*/
#define CCI_CCI_I2C_M1_Q1_CUR_CMD_CUR_CMD_MASK 0xffffffff
#define CCI_CCI_I2C_M1_Q1_CUR_CMD_CUR_CMD_SHIFT 0x0

#define regCCI_CCI_I2C_M1_Q1_REPORT_STATUS 0x60c  /*register offset*/
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_LINE_CNT_MASK 0x3fff
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_LINE_CNT_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_UNUSED0_MASK 0xc000
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_UNUSED0_SHIFT 0xe
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_FRAME_CNT_MASK 0xff0000
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_FRAME_CNT_SHIFT 0x10
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_CID_MASK 0xf000000
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_CID_SHIFT 0x18
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_REPORT_ID_MASK 0xf0000000
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_REPORT_ID_SHIFT 0x1c

#define regCCI_CCI_I2C_M1_Q1_LOAD_DATA 0x610  /*register offset*/
#define CCI_CCI_I2C_M1_Q1_LOAD_DATA_LOAD_DATA_MASK 0xffffffff
#define CCI_CCI_I2C_M1_Q1_LOAD_DATA_LOAD_DATA_SHIFT 0x0

#define regCCI_CCI_I2C_M1_Q1_DEBUG_INFO 0x614  /*register offset*/
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_SLAVE_ID_MASK 0x7f
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_SLAVE_ID_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_UNUSED0_MASK 0xf80
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_UNUSED0_SHIFT 0x7
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_RETRY_CNT_MASK 0x3000
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_RETRY_CNT_SHIFT 0xc
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_CSI_SENSOR_SYNC_ID_MASK 0xc000
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_CSI_SENSOR_SYNC_ID_SHIFT 0xe
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_UNUSED1_MASK 0xffff0000
#define CCI_CCI_I2C_M1_Q1_DEBUG_INFO_UNUSED1_SHIFT 0x10

#define regCCI_CCI_I2C_M1_Q1_REPORT_STATUS_1 0x618  /*register offset*/
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_1_CID_MASK 0x7f
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_1_CID_SHIFT 0x0
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_1_UNUSED0_MASK 0xffffff80
#define CCI_CCI_I2C_M1_Q1_REPORT_STATUS_1_UNUSED0_SHIFT 0x7

#define regCCI_CCI_GPIO_Q0_EXEC_WORD_CNT 0x700  /*register offset*/
#define CCI_CCI_GPIO_Q0_EXEC_WORD_CNT_EXEC_WORD_CNT_MASK 0x3f
#define CCI_CCI_GPIO_Q0_EXEC_WORD_CNT_EXEC_WORD_CNT_SHIFT 0x0
#define CCI_CCI_GPIO_Q0_EXEC_WORD_CNT_UNUSED0_MASK 0xffffffc0
#define CCI_CCI_GPIO_Q0_EXEC_WORD_CNT_UNUSED0_SHIFT 0x6

#define regCCI_CCI_GPIO_Q0_CUR_WORD_CNT 0x704  /*register offset*/
#define CCI_CCI_GPIO_Q0_CUR_WORD_CNT_CUR_WORD_CNT_MASK 0x3f
#define CCI_CCI_GPIO_Q0_CUR_WORD_CNT_CUR_WORD_CNT_SHIFT 0x0
#define CCI_CCI_GPIO_Q0_CUR_WORD_CNT_UNUSED0_MASK 0xffffffc0
#define CCI_CCI_GPIO_Q0_CUR_WORD_CNT_UNUSED0_SHIFT 0x6

#define regCCI_CCI_GPIO_Q0_CUR_CMD 0x708  /*register offset*/
#define CCI_CCI_GPIO_Q0_CUR_CMD_CUR_CMD_MASK 0xffffffff
#define CCI_CCI_GPIO_Q0_CUR_CMD_CUR_CMD_SHIFT 0x0

#define regCCI_CCI_GPIO_Q0_REPORT_STATUS 0x70c  /*register offset*/
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_LINE_CNT_MASK 0x3fff
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_LINE_CNT_SHIFT 0x0
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_UNUSED0_MASK 0xc000
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_UNUSED0_SHIFT 0xe
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_FRAME_CNT_MASK 0xff0000
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_FRAME_CNT_SHIFT 0x10
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_CID_MASK 0xf000000
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_CID_SHIFT 0x18
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_REPORT_ID_MASK 0xf0000000
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_REPORT_ID_SHIFT 0x1c

#define regCCI_CCI_GPIO_Q0_LOAD_DATA 0x710  /*register offset*/
#define CCI_CCI_GPIO_Q0_LOAD_DATA_LOAD_DATA_MASK 0xffffffff
#define CCI_CCI_GPIO_Q0_LOAD_DATA_LOAD_DATA_SHIFT 0x0

#define regCCI_CCI_GPIO_Q0_REPORT_STATUS_1 0x714  /*register offset*/
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_1_CID_MASK 0x7f
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_1_CID_SHIFT 0x0
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_1_UNUSED0_MASK 0xffffff80
#define CCI_CCI_GPIO_Q0_REPORT_STATUS_1_UNUSED0_SHIFT 0x7

#define regCCI_CCI_GPIO_Q1_EXEC_WORD_CNT 0x800  /*register offset*/
#define CCI_CCI_GPIO_Q1_EXEC_WORD_CNT_EXEC_WORD_CNT_MASK 0x1f
#define CCI_CCI_GPIO_Q1_EXEC_WORD_CNT_EXEC_WORD_CNT_SHIFT 0x0
#define CCI_CCI_GPIO_Q1_EXEC_WORD_CNT_UNUSED0_MASK 0xffffffe0
#define CCI_CCI_GPIO_Q1_EXEC_WORD_CNT_UNUSED0_SHIFT 0x5

#define regCCI_CCI_GPIO_Q1_CUR_WORD_CNT 0x804  /*register offset*/
#define CCI_CCI_GPIO_Q1_CUR_WORD_CNT_CUR_WORD_CNT_MASK 0x1f
#define CCI_CCI_GPIO_Q1_CUR_WORD_CNT_CUR_WORD_CNT_SHIFT 0x0
#define CCI_CCI_GPIO_Q1_CUR_WORD_CNT_UNUSED0_MASK 0xffffffe0
#define CCI_CCI_GPIO_Q1_CUR_WORD_CNT_UNUSED0_SHIFT 0x5

#define regCCI_CCI_GPIO_Q1_CUR_CMD 0x808  /*register offset*/
#define CCI_CCI_GPIO_Q1_CUR_CMD_CUR_CMD_MASK 0xffffffff
#define CCI_CCI_GPIO_Q1_CUR_CMD_CUR_CMD_SHIFT 0x0

#define regCCI_CCI_GPIO_Q1_REPORT_STATUS 0x80c  /*register offset*/
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_LINE_CNT_MASK 0x3fff
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_LINE_CNT_SHIFT 0x0
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_UNUSED0_MASK 0xc000
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_UNUSED0_SHIFT 0xe
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_FRAME_CNT_MASK 0xff0000
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_FRAME_CNT_SHIFT 0x10
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_CID_MASK 0xf000000
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_CID_SHIFT 0x18
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_REPORT_ID_MASK 0xf0000000
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_REPORT_ID_SHIFT 0x1c

#define regCCI_CCI_GPIO_Q1_LOAD_DATA 0x810  /*register offset*/
#define CCI_CCI_GPIO_Q1_LOAD_DATA_LOAD_DATA_MASK 0xffffffff
#define CCI_CCI_GPIO_Q1_LOAD_DATA_LOAD_DATA_SHIFT 0x0

#define regCCI_CCI_GPIO_Q1_REPORT_STATUS_1 0x814  /*register offset*/
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_1_CID_MASK 0x7f
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_1_CID_SHIFT 0x0
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_1_UNUSED0_MASK 0xffffff80
#define CCI_CCI_GPIO_Q1_REPORT_STATUS_1_UNUSED0_SHIFT 0x7

#define regCCI_CCI_GPIO_Q2_EXEC_WORD_CNT 0x900  /*register offset*/
#define CCI_CCI_GPIO_Q2_EXEC_WORD_CNT_EXEC_WORD_CNT_MASK 0x1f
#define CCI_CCI_GPIO_Q2_EXEC_WORD_CNT_EXEC_WORD_CNT_SHIFT 0x0
#define CCI_CCI_GPIO_Q2_EXEC_WORD_CNT_UNUSED0_MASK 0xffffffe0
#define CCI_CCI_GPIO_Q2_EXEC_WORD_CNT_UNUSED0_SHIFT 0x5

#define regCCI_CCI_GPIO_Q2_CUR_WORD_CNT 0x904  /*register offset*/
#define CCI_CCI_GPIO_Q2_CUR_WORD_CNT_CUR_WORD_CNT_MASK 0x1f
#define CCI_CCI_GPIO_Q2_CUR_WORD_CNT_CUR_WORD_CNT_SHIFT 0x0
#define CCI_CCI_GPIO_Q2_CUR_WORD_CNT_UNUSED0_MASK 0xffffffe0
#define CCI_CCI_GPIO_Q2_CUR_WORD_CNT_UNUSED0_SHIFT 0x5

#define regCCI_CCI_GPIO_Q2_CUR_CMD 0x908  /*register offset*/
#define CCI_CCI_GPIO_Q2_CUR_CMD_CUR_CMD_MASK 0xffffffff
#define CCI_CCI_GPIO_Q2_CUR_CMD_CUR_CMD_SHIFT 0x0

#define regCCI_CCI_GPIO_Q2_REPORT_STATUS 0x90c  /*register offset*/
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_LINE_CNT_MASK 0x3fff
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_LINE_CNT_SHIFT 0x0
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_UNUSED0_MASK 0xc000
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_UNUSED0_SHIFT 0xe
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_FRAME_CNT_MASK 0xff0000
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_FRAME_CNT_SHIFT 0x10
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_CID_MASK 0xf000000
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_CID_SHIFT 0x18
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_REPORT_ID_MASK 0xf0000000
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_REPORT_ID_SHIFT 0x1c

#define regCCI_CCI_GPIO_Q2_LOAD_DATA 0x910  /*register offset*/
#define CCI_CCI_GPIO_Q2_LOAD_DATA_LOAD_DATA_MASK 0xffffffff
#define CCI_CCI_GPIO_Q2_LOAD_DATA_LOAD_DATA_SHIFT 0x0

#define regCCI_CCI_GPIO_Q2_REPORT_STATUS_1 0x914  /*register offset*/
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_1_CID_MASK 0x7f
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_1_CID_SHIFT 0x0
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_1_UNUSED0_MASK 0xffffff80
#define CCI_CCI_GPIO_Q2_REPORT_STATUS_1_UNUSED0_SHIFT 0x7

#define regCCI_CCI_IRQ_GLOBAL_CLEAR_CMD 0xc00  /*register offset*/
#define CCI_CCI_IRQ_GLOBAL_CLEAR_CMD_GLOBAL_CLEAR_MASK 0x1
#define CCI_CCI_IRQ_GLOBAL_CLEAR_CMD_GLOBAL_CLEAR_SHIFT 0x0
#define CCI_CCI_IRQ_GLOBAL_CLEAR_CMD_UNUSED0_MASK 0xfffffffe
#define CCI_CCI_IRQ_GLOBAL_CLEAR_CMD_UNUSED0_SHIFT 0x1

#define regCCI_CCI_IRQ_MASK_0 0xc04  /*register offset*/
#define CCI_CCI_IRQ_MASK_0_I2C_M0_RD_DONE_MASK 0x1
#define CCI_CCI_IRQ_MASK_0_I2C_M0_RD_DONE_SHIFT 0x0
#define CCI_CCI_IRQ_MASK_0_I2C_M0_RD_UNDERFLOW_MASK 0x2
#define CCI_CCI_IRQ_MASK_0_I2C_M0_RD_UNDERFLOW_SHIFT 0x1
#define CCI_CCI_IRQ_MASK_0_I2C_M0_RD_OVERFLOW_MASK 0x4
#define CCI_CCI_IRQ_MASK_0_I2C_M0_RD_OVERFLOW_SHIFT 0x2
#define CCI_CCI_IRQ_MASK_0_UNUSED0_MASK 0x8
#define CCI_CCI_IRQ_MASK_0_UNUSED0_SHIFT 0x3
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT_MASK 0x10
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT_SHIFT 0x4
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_UNDERFLOW_MASK 0x20
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_UNDERFLOW_SHIFT 0x5
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_OVERFLOW_MASK 0x40
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_OVERFLOW_SHIFT 0x6
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_CMD_ERR_MASK 0x80
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_CMD_ERR_SHIFT 0x7
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT_MASK 0x100
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT_SHIFT 0x8
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_UNDERFLOW_MASK 0x200
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_UNDERFLOW_SHIFT 0x9
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_OVERFLOW_MASK 0x400
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_OVERFLOW_SHIFT 0xa
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_CMD_ERR_MASK 0x800
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_CMD_ERR_SHIFT 0xb
#define CCI_CCI_IRQ_MASK_0_I2C_M1_RD_DONE_MASK 0x1000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_RD_DONE_SHIFT 0xc
#define CCI_CCI_IRQ_MASK_0_I2C_M1_RD_UNDERFLOW_MASK 0x2000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_RD_UNDERFLOW_SHIFT 0xd
#define CCI_CCI_IRQ_MASK_0_I2C_M1_RD_OVERFLOW_MASK 0x4000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_RD_OVERFLOW_SHIFT 0xe
#define CCI_CCI_IRQ_MASK_0_UNUSED1_MASK 0x8000
#define CCI_CCI_IRQ_MASK_0_UNUSED1_SHIFT 0xf
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT_MASK 0x10000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT_SHIFT 0x10
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_UNDERFLOW_MASK 0x20000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_UNDERFLOW_SHIFT 0x11
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_OVERFLOW_MASK 0x40000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_OVERFLOW_SHIFT 0x12
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_CMD_ERR_MASK 0x80000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_CMD_ERR_SHIFT 0x13
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT_MASK 0x100000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT_SHIFT 0x14
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_UNDERFLOW_MASK 0x200000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_UNDERFLOW_SHIFT 0x15
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_OVERFLOW_MASK 0x400000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_OVERFLOW_SHIFT 0x16
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_CMD_ERR_MASK 0x800000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_CMD_ERR_SHIFT 0x17
#define CCI_CCI_IRQ_MASK_0_RST_DONE_ACK_MASK 0x1000000
#define CCI_CCI_IRQ_MASK_0_RST_DONE_ACK_SHIFT 0x18
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK_MASK 0x2000000
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK_SHIFT 0x19
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK_MASK 0x4000000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK_SHIFT 0x1a
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_NACK_ERR_MASK 0x8000000
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q0_NACK_ERR_SHIFT 0x1b
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_NACK_ERR_MASK 0x10000000
#define CCI_CCI_IRQ_MASK_0_I2C_M0_Q1_NACK_ERR_SHIFT 0x1c
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_NACK_ERR_MASK 0x20000000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q0_NACK_ERR_SHIFT 0x1d
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_NACK_ERR_MASK 0x40000000
#define CCI_CCI_IRQ_MASK_0_I2C_M1_Q1_NACK_ERR_SHIFT 0x1e
#define CCI_CCI_IRQ_MASK_0_UNUSED2_MASK 0x80000000
#define CCI_CCI_IRQ_MASK_0_UNUSED2_SHIFT 0x1f

#define regCCI_CCI_IRQ_CLEAR_0 0xc08  /*register offset*/
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_RD_DONE_MASK 0x1
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_RD_DONE_SHIFT 0x0
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_RD_UNDERFLOW_MASK 0x2
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_RD_UNDERFLOW_SHIFT 0x1
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_RD_OVERFLOW_MASK 0x4
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_RD_OVERFLOW_SHIFT 0x2
#define CCI_CCI_IRQ_CLEAR_0_UNUSED0_MASK 0x8
#define CCI_CCI_IRQ_CLEAR_0_UNUSED0_SHIFT 0x3
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_REPORT_MASK 0x10
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_REPORT_SHIFT 0x4
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_UNDERFLOW_MASK 0x20
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_UNDERFLOW_SHIFT 0x5
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_OVERFLOW_MASK 0x40
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_OVERFLOW_SHIFT 0x6
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_CMD_ERR_MASK 0x80
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_CMD_ERR_SHIFT 0x7
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_REPORT_MASK 0x100
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_REPORT_SHIFT 0x8
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_UNDERFLOW_MASK 0x200
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_UNDERFLOW_SHIFT 0x9
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_OVERFLOW_MASK 0x400
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_OVERFLOW_SHIFT 0xa
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_CMD_ERR_MASK 0x800
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_CMD_ERR_SHIFT 0xb
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_RD_DONE_MASK 0x1000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_RD_DONE_SHIFT 0xc
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_RD_UNDERFLOW_MASK 0x2000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_RD_UNDERFLOW_SHIFT 0xd
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_RD_OVERFLOW_MASK 0x4000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_RD_OVERFLOW_SHIFT 0xe
#define CCI_CCI_IRQ_CLEAR_0_UNUSED1_MASK 0x8000
#define CCI_CCI_IRQ_CLEAR_0_UNUSED1_SHIFT 0xf
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_REPORT_MASK 0x10000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_REPORT_SHIFT 0x10
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_UNDERFLOW_MASK 0x20000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_UNDERFLOW_SHIFT 0x11
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_OVERFLOW_MASK 0x40000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_OVERFLOW_SHIFT 0x12
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_CMD_ERR_MASK 0x80000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_CMD_ERR_SHIFT 0x13
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_REPORT_MASK 0x100000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_REPORT_SHIFT 0x14
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_UNDERFLOW_MASK 0x200000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_UNDERFLOW_SHIFT 0x15
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_OVERFLOW_MASK 0x400000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_OVERFLOW_SHIFT 0x16
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_CMD_ERR_MASK 0x800000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_CMD_ERR_SHIFT 0x17
#define CCI_CCI_IRQ_CLEAR_0_RST_DONE_ACK_MASK 0x1000000
#define CCI_CCI_IRQ_CLEAR_0_RST_DONE_ACK_SHIFT 0x18
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0Q1_HALT_ACK_MASK 0x2000000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0Q1_HALT_ACK_SHIFT 0x19
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0Q1_HALT_ACK_MASK 0x4000000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0Q1_HALT_ACK_SHIFT 0x1a
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_NACK_ERR_MASK 0x8000000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q0_NACK_ERR_SHIFT 0x1b
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_NACK_ERR_MASK 0x10000000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M0_Q1_NACK_ERR_SHIFT 0x1c
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_NACK_ERR_MASK 0x20000000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q0_NACK_ERR_SHIFT 0x1d
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_NACK_ERR_MASK 0x40000000
#define CCI_CCI_IRQ_CLEAR_0_I2C_M1_Q1_NACK_ERR_SHIFT 0x1e
#define CCI_CCI_IRQ_CLEAR_0_UNUSED2_MASK 0x80000000
#define CCI_CCI_IRQ_CLEAR_0_UNUSED2_SHIFT 0x1f

#define regCCI_CCI_IRQ_STATUS_0 0xc0c  /*register offset*/
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_MASK 0x1
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_SHIFT 0x0
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_RD_UNDERFLOW_MASK 0x2
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_RD_UNDERFLOW_SHIFT 0x1
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_RD_OVERFLOW_MASK 0x4
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_RD_OVERFLOW_SHIFT 0x2
#define CCI_CCI_IRQ_STATUS_0_UNUSED0_MASK 0x8
#define CCI_CCI_IRQ_STATUS_0_UNUSED0_SHIFT 0x3
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT_MASK 0x10
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT_SHIFT 0x4
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_UNDERFLOW_MASK 0x20
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_UNDERFLOW_SHIFT 0x5
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_OVERFLOW_MASK 0x40
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_OVERFLOW_SHIFT 0x6
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_CMD_ERR_MASK 0x80
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_CMD_ERR_SHIFT 0x7
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT_MASK 0x100
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT_SHIFT 0x8
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_UNDERFLOW_MASK 0x200
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_UNDERFLOW_SHIFT 0x9
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_OVERFLOW_MASK 0x400
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_OVERFLOW_SHIFT 0xa
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_CMD_ERR_MASK 0x800
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_CMD_ERR_SHIFT 0xb
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_MASK 0x1000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_SHIFT 0xc
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_RD_UNDERFLOW_MASK 0x2000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_RD_UNDERFLOW_SHIFT 0xd
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_RD_OVERFLOW_MASK 0x4000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_RD_OVERFLOW_SHIFT 0xe
#define CCI_CCI_IRQ_STATUS_0_UNUSED1_MASK 0x8000
#define CCI_CCI_IRQ_STATUS_0_UNUSED1_SHIFT 0xf
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT_MASK 0x10000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT_SHIFT 0x10
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_UNDERFLOW_MASK 0x20000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_UNDERFLOW_SHIFT 0x11
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_OVERFLOW_MASK 0x40000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_OVERFLOW_SHIFT 0x12
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_CMD_ERR_MASK 0x80000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_CMD_ERR_SHIFT 0x13
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT_MASK 0x100000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT_SHIFT 0x14
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_UNDERFLOW_MASK 0x200000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_UNDERFLOW_SHIFT 0x15
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_OVERFLOW_MASK 0x400000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_OVERFLOW_SHIFT 0x16
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_CMD_ERR_MASK 0x800000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_CMD_ERR_SHIFT 0x17
#define CCI_CCI_IRQ_STATUS_0_RST_DONE_ACK_MASK 0x1000000
#define CCI_CCI_IRQ_STATUS_0_RST_DONE_ACK_SHIFT 0x18
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_MASK 0x2000000
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_SHIFT 0x19
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_MASK 0x4000000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_SHIFT 0x1a
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR_MASK 0x8000000
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR_SHIFT 0x1b
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR_MASK 0x10000000
#define CCI_CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR_SHIFT 0x1c
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR_MASK 0x20000000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR_SHIFT 0x1d
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR_MASK 0x40000000
#define CCI_CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR_SHIFT 0x1e
#define CCI_CCI_IRQ_STATUS_0_UNUSED2_MASK 0x80000000
#define CCI_CCI_IRQ_STATUS_0_UNUSED2_SHIFT 0x1f

#define regCCI_CCI_IRQ_MASK_1 0xc10  /*register offset*/
#define CCI_CCI_IRQ_MASK_1_GPIO_Q0_REPORT_MASK 0x1
#define CCI_CCI_IRQ_MASK_1_GPIO_Q0_REPORT_SHIFT 0x0
#define CCI_CCI_IRQ_MASK_1_GPIO_Q0_UNDERFLOW_MASK 0x2
#define CCI_CCI_IRQ_MASK_1_GPIO_Q0_UNDERFLOW_SHIFT 0x1
#define CCI_CCI_IRQ_MASK_1_GPIO_Q0_OVERFLOW_MASK 0x4
#define CCI_CCI_IRQ_MASK_1_GPIO_Q0_OVERFLOW_SHIFT 0x2
#define CCI_CCI_IRQ_MASK_1_GPIO_Q0_CMD_ERR_MASK 0x8
#define CCI_CCI_IRQ_MASK_1_GPIO_Q0_CMD_ERR_SHIFT 0x3
#define CCI_CCI_IRQ_MASK_1_GPIO_Q1_REPORT_MASK 0x10
#define CCI_CCI_IRQ_MASK_1_GPIO_Q1_REPORT_SHIFT 0x4
#define CCI_CCI_IRQ_MASK_1_GPIO_Q1_UNDERFLOW_MASK 0x20
#define CCI_CCI_IRQ_MASK_1_GPIO_Q1_UNDERFLOW_SHIFT 0x5
#define CCI_CCI_IRQ_MASK_1_GPIO_Q1_OVERFLOW_MASK 0x40
#define CCI_CCI_IRQ_MASK_1_GPIO_Q1_OVERFLOW_SHIFT 0x6
#define CCI_CCI_IRQ_MASK_1_GPIO_Q1_CMD_ERR_MASK 0x80
#define CCI_CCI_IRQ_MASK_1_GPIO_Q1_CMD_ERR_SHIFT 0x7
#define CCI_CCI_IRQ_MASK_1_GPIO_Q2_REPORT_MASK 0x100
#define CCI_CCI_IRQ_MASK_1_GPIO_Q2_REPORT_SHIFT 0x8
#define CCI_CCI_IRQ_MASK_1_GPIO_Q2_UNDERFLOW_MASK 0x200
#define CCI_CCI_IRQ_MASK_1_GPIO_Q2_UNDERFLOW_SHIFT 0x9
#define CCI_CCI_IRQ_MASK_1_GPIO_Q2_OVERFLOW_MASK 0x400
#define CCI_CCI_IRQ_MASK_1_GPIO_Q2_OVERFLOW_SHIFT 0xa
#define CCI_CCI_IRQ_MASK_1_GPIO_Q2_CMD_ERR_MASK 0x800
#define CCI_CCI_IRQ_MASK_1_GPIO_Q2_CMD_ERR_SHIFT 0xb
#define CCI_CCI_IRQ_MASK_1_UNUSED0_MASK 0xf000
#define CCI_CCI_IRQ_MASK_1_UNUSED0_SHIFT 0xc
#define CCI_CCI_IRQ_MASK_1_I2C_M0_RD_THRESHOLD_MASK 0x10000
#define CCI_CCI_IRQ_MASK_1_I2C_M0_RD_THRESHOLD_SHIFT 0x10
#define CCI_CCI_IRQ_MASK_1_I2C_M0_RD_PAUSE_MASK 0x20000
#define CCI_CCI_IRQ_MASK_1_I2C_M0_RD_PAUSE_SHIFT 0x11
#define CCI_CCI_IRQ_MASK_1_I2C_M0_Q0_CMD_THRESHOLD_MASK 0x40000
#define CCI_CCI_IRQ_MASK_1_I2C_M0_Q0_CMD_THRESHOLD_SHIFT 0x12
#define CCI_CCI_IRQ_MASK_1_I2C_M0_Q1_CMD_THRESHOLD_MASK 0x80000
#define CCI_CCI_IRQ_MASK_1_I2C_M0_Q1_CMD_THRESHOLD_SHIFT 0x13
#define CCI_CCI_IRQ_MASK_1_I2C_M1_RD_THRESHOLD_MASK 0x100000
#define CCI_CCI_IRQ_MASK_1_I2C_M1_RD_THRESHOLD_SHIFT 0x14
#define CCI_CCI_IRQ_MASK_1_I2C_M1_RD_PAUSE_MASK 0x200000
#define CCI_CCI_IRQ_MASK_1_I2C_M1_RD_PAUSE_SHIFT 0x15
#define CCI_CCI_IRQ_MASK_1_I2C_M1_Q0_CMD_THRESHOLD_MASK 0x400000
#define CCI_CCI_IRQ_MASK_1_I2C_M1_Q0_CMD_THRESHOLD_SHIFT 0x16
#define CCI_CCI_IRQ_MASK_1_I2C_M1_Q1_CMD_THRESHOLD_MASK 0x800000
#define CCI_CCI_IRQ_MASK_1_I2C_M1_Q1_CMD_THRESHOLD_SHIFT 0x17
#define CCI_CCI_IRQ_MASK_1_UNUSED1_MASK 0xff000000
#define CCI_CCI_IRQ_MASK_1_UNUSED1_SHIFT 0x18

#define regCCI_CCI_IRQ_CLEAR_1 0xc14  /*register offset*/
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q0_REPORT_MASK 0x1
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q0_REPORT_SHIFT 0x0
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q0_UNDERFLOW_MASK 0x2
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q0_UNDERFLOW_SHIFT 0x1
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q0_OVERFLOW_MASK 0x4
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q0_OVERFLOW_SHIFT 0x2
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q0_CMD_ERR_MASK 0x8
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q0_CMD_ERR_SHIFT 0x3
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q1_REPORT_MASK 0x10
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q1_REPORT_SHIFT 0x4
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q1_UNDERFLOW_MASK 0x20
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q1_UNDERFLOW_SHIFT 0x5
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q1_OVERFLOW_MASK 0x40
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q1_OVERFLOW_SHIFT 0x6
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q1_CMD_ERR_MASK 0x80
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q1_CMD_ERR_SHIFT 0x7
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q2_REPORT_MASK 0x100
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q2_REPORT_SHIFT 0x8
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q2_UNDERFLOW_MASK 0x200
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q2_UNDERFLOW_SHIFT 0x9
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q2_OVERFLOW_MASK 0x400
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q2_OVERFLOW_SHIFT 0xa
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q2_CMD_ERR_MASK 0x800
#define CCI_CCI_IRQ_CLEAR_1_GPIO_Q2_CMD_ERR_SHIFT 0xb
#define CCI_CCI_IRQ_CLEAR_1_UNUSED0_MASK 0xf000
#define CCI_CCI_IRQ_CLEAR_1_UNUSED0_SHIFT 0xc
#define CCI_CCI_IRQ_CLEAR_1_I2C_M0_RD_THRESHOLD_MASK 0x10000
#define CCI_CCI_IRQ_CLEAR_1_I2C_M0_RD_THRESHOLD_SHIFT 0x10
#define CCI_CCI_IRQ_CLEAR_1_I2C_M0_RD_PAUSE_MASK 0x20000
#define CCI_CCI_IRQ_CLEAR_1_I2C_M0_RD_PAUSE_SHIFT 0x11
#define CCI_CCI_IRQ_CLEAR_1_I2C_M0_Q0_CMD_THRESHOLD_MASK 0x40000
#define CCI_CCI_IRQ_CLEAR_1_I2C_M0_Q0_CMD_THRESHOLD_SHIFT 0x12
#define CCI_CCI_IRQ_CLEAR_1_I2C_M0_Q1_CMD_THRESHOLD_MASK 0x80000
#define CCI_CCI_IRQ_CLEAR_1_I2C_M0_Q1_CMD_THRESHOLD_SHIFT 0x13
#define CCI_CCI_IRQ_CLEAR_1_I2C_M1_RD_THRESHOLD_MASK 0x100000
#define CCI_CCI_IRQ_CLEAR_1_I2C_M1_RD_THRESHOLD_SHIFT 0x14
#define CCI_CCI_IRQ_CLEAR_1_I2C_M1_RD_PAUSE_MASK 0x200000
#define CCI_CCI_IRQ_CLEAR_1_I2C_M1_RD_PAUSE_SHIFT 0x15
#define CCI_CCI_IRQ_CLEAR_1_I2C_M1_Q0_CMD_THRESHOLD_MASK 0x400000
#define CCI_CCI_IRQ_CLEAR_1_I2C_M1_Q0_CMD_THRESHOLD_SHIFT 0x16
#define CCI_CCI_IRQ_CLEAR_1_I2C_M1_Q1_CMD_THRESHOLD_MASK 0x800000
#define CCI_CCI_IRQ_CLEAR_1_I2C_M1_Q1_CMD_THRESHOLD_SHIFT 0x17
#define CCI_CCI_IRQ_CLEAR_1_UNUSED1_MASK 0xff000000
#define CCI_CCI_IRQ_CLEAR_1_UNUSED1_SHIFT 0x18

#define regCCI_CCI_IRQ_STATUS_1 0xc18  /*register offset*/
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q0_REPORT_MASK 0x1
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q0_REPORT_SHIFT 0x0
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q0_UNDERFLOW_MASK 0x2
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q0_UNDERFLOW_SHIFT 0x1
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q0_OVERFLOW_MASK 0x4
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q0_OVERFLOW_SHIFT 0x2
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q0_CMD_ERR_MASK 0x8
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q0_CMD_ERR_SHIFT 0x3
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q1_REPORT_MASK 0x10
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q1_REPORT_SHIFT 0x4
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q1_UNDERFLOW_MASK 0x20
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q1_UNDERFLOW_SHIFT 0x5
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q1_OVERFLOW_MASK 0x40
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q1_OVERFLOW_SHIFT 0x6
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q1_CMD_ERR_MASK 0x80
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q1_CMD_ERR_SHIFT 0x7
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q2_REPORT_MASK 0x100
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q2_REPORT_SHIFT 0x8
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q2_UNDERFLOW_MASK 0x200
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q2_UNDERFLOW_SHIFT 0x9
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q2_OVERFLOW_MASK 0x400
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q2_OVERFLOW_SHIFT 0xa
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q2_CMD_ERR_MASK 0x800
#define CCI_CCI_IRQ_STATUS_1_GPIO_Q2_CMD_ERR_SHIFT 0xb
#define CCI_CCI_IRQ_STATUS_1_UNUSED0_MASK 0xf000
#define CCI_CCI_IRQ_STATUS_1_UNUSED0_SHIFT 0xc
#define CCI_CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD_MASK 0x10000
#define CCI_CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD_SHIFT 0x10
#define CCI_CCI_IRQ_STATUS_1_I2C_M0_RD_PAUSE_MASK 0x20000
#define CCI_CCI_IRQ_STATUS_1_I2C_M0_RD_PAUSE_SHIFT 0x11
#define CCI_CCI_IRQ_STATUS_1_I2C_M0_Q0_CMD_THRESHOLD_MASK 0x40000
#define CCI_CCI_IRQ_STATUS_1_I2C_M0_Q0_CMD_THRESHOLD_SHIFT 0x12
#define CCI_CCI_IRQ_STATUS_1_I2C_M0_Q1_CMD_THRESHOLD_MASK 0x80000
#define CCI_CCI_IRQ_STATUS_1_I2C_M0_Q1_CMD_THRESHOLD_SHIFT 0x13
#define CCI_CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD_MASK 0x100000
#define CCI_CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD_SHIFT 0x14
#define CCI_CCI_IRQ_STATUS_1_I2C_M1_RD_PAUSE_MASK 0x200000
#define CCI_CCI_IRQ_STATUS_1_I2C_M1_RD_PAUSE_SHIFT 0x15
#define CCI_CCI_IRQ_STATUS_1_I2C_M1_Q0_CMD_THRESHOLD_MASK 0x400000
#define CCI_CCI_IRQ_STATUS_1_I2C_M1_Q0_CMD_THRESHOLD_SHIFT 0x16
#define CCI_CCI_IRQ_STATUS_1_I2C_M1_Q1_CMD_THRESHOLD_MASK 0x800000
#define CCI_CCI_IRQ_STATUS_1_I2C_M1_Q1_CMD_THRESHOLD_SHIFT 0x17
#define CCI_CCI_IRQ_STATUS_1_UNUSED1_MASK 0xff000000
#define CCI_CCI_IRQ_STATUS_1_UNUSED1_SHIFT 0x18

/*----------------------------------------------------------------------
        Register Data Structures
----------------------------------------------------------------------*/

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR_VERSION : 12; /* 27:16 */
    unsigned  MAJOR_VERSION : 4; /* 31:28 */
} _cci_cci_hw_version;

typedef union{
    _cci_cci_hw_version bitfields,bits;
    unsigned int u32All;

} CCI_CCI_HW_VERSION;

typedef struct{
    unsigned  STROBED_RST_EN : 1; /* 0:0 */
    unsigned  MISC_LOGIC_RST_STB : 1; /* 1:1 */
    unsigned  SW_REG_RST_STB : 1; /* 2:2 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  I2C_M0_RST_STB : 1; /* 4:4 */
    unsigned  I2C_M0_RD_FIFO_RST_STB : 1; /* 5:5 */
    unsigned  I2C_M0_QCMD_PROC_RST_STB : 1; /* 6:6 */
    unsigned  I2C_M0_QARB_RST_STB : 1; /* 7:7 */
    unsigned  I2C_M0_Q0_RST_STB : 1; /* 8:8 */
    unsigned  I2C_M0_Q1_RST_STB : 1; /* 9:9 */
    unsigned  UNUSED1 : 2; /* 11:10 */
    unsigned  I2C_M1_RST_STB : 1; /* 12:12 */
    unsigned  I2C_M1_RD_FIFO_RST_STB : 1; /* 13:13 */
    unsigned  I2C_M1_QCMD_PROC_RST_STB : 1; /* 14:14 */
    unsigned  I2C_M1_QARB_RST_STB : 1; /* 15:15 */
    unsigned  I2C_M1_Q0_RST_STB : 1; /* 16:16 */
    unsigned  I2C_M1_Q1_RST_STB : 1; /* 17:17 */
    unsigned  UNUSED2 : 2; /* 19:18 */
    unsigned  GPIO_Q0_RST_STB : 1; /* 20:20 */
    unsigned  GPIO_Q1_RST_STB : 1; /* 21:21 */
    unsigned  GPIO_Q2_RST_STB : 1; /* 22:22 */
    unsigned  UNUSED3 : 1; /* 23:23 */
    unsigned  SYNC_TIMER_0_RST_STB : 1; /* 24:24 */
    unsigned  SYNC_TIMER_1_RST_STB : 1; /* 25:25 */
    unsigned  SYNC_TIMER_2_RST_STB : 1; /* 26:26 */
    unsigned  SYNC_TIMER_3_RST_STB : 1; /* 27:27 */
    unsigned  UNUSED4 : 2; /* 29:28 */
    unsigned  CCI_CLK_DOMAIN_RST : 1; /* 30:30 */
    unsigned  AHB_CLK_DOMAIN_RST : 1; /* 31:31 */
} _cci_cci_reset_cmd;

typedef union{
    _cci_cci_reset_cmd bitfields,bits;
    unsigned int u32All;

} CCI_CCI_RESET_CMD;

typedef struct{
    unsigned  I2C_M0_Q0_START : 1; /* 0:0 */
    unsigned  I2C_M0_Q1_START : 1; /* 1:1 */
    unsigned  I2C_M1_Q0_START : 1; /* 2:2 */
    unsigned  I2C_M1_Q1_START : 1; /* 3:3 */
    unsigned  GPIO_Q0_START : 1; /* 4:4 */
    unsigned  GPIO_Q1_START : 1; /* 5:5 */
    unsigned  GPIO_Q2_START : 1; /* 6:6 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_queue_start;

typedef union{
    _cci_cci_queue_start bitfields,bits;
    unsigned int u32All;

} CCI_CCI_QUEUE_START;

typedef struct{
    unsigned  TESTBUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TESTBUS_SEL : 24; /* 27:4 */
    unsigned  DOMAIN_SEL : 1; /* 28:28 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _cci_cci_testbus_sel;

typedef union{
    _cci_cci_testbus_sel bitfields,bits;
    unsigned int u32All;

} CCI_CCI_TESTBUS_SEL;

typedef struct{
    unsigned  SENSOR_SYNC_CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_set_cid_sync_timer_0;

typedef union{
    _cci_cci_set_cid_sync_timer_0 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_SET_CID_SYNC_TIMER_0;

typedef struct{
    unsigned  SENSOR_SYNC_CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_set_cid_sync_timer_1;

typedef union{
    _cci_cci_set_cid_sync_timer_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_SET_CID_SYNC_TIMER_1;

typedef struct{
    unsigned  SENSOR_SYNC_CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_set_cid_sync_timer_2;

typedef union{
    _cci_cci_set_cid_sync_timer_2 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_SET_CID_SYNC_TIMER_2;

typedef struct{
    unsigned  SENSOR_SYNC_CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_set_cid_sync_timer_3;

typedef union{
    _cci_cci_set_cid_sync_timer_3 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_SET_CID_SYNC_TIMER_3;

typedef struct{
    unsigned  GPIO_IN0 : 1; /* 0:0 */
    unsigned  GPIO_IN1 : 1; /* 1:1 */
    unsigned  GPIO_IN2 : 1; /* 2:2 */
    unsigned  UNUSED0 : 5; /* 7:3 */
    unsigned  GPIO_OUT0 : 1; /* 8:8 */
    unsigned  GPIO_OUT1 : 1; /* 9:9 */
    unsigned  GPIO_OUT2 : 1; /* 10:10 */
    unsigned  GPIO_OUT3 : 1; /* 11:11 */
    unsigned  GPIO_OUT4 : 1; /* 12:12 */
    unsigned  UNUSED1 : 19; /* 31:13 */
} _cci_cci_gpio_status;

typedef union{
    _cci_cci_gpio_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_STATUS;

typedef struct{
    unsigned  I2C_M0_Q0Q1_HALT_REQ : 1; /* 0:0 */
    unsigned  I2C_M1_Q0Q1_HALT_REQ : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _cci_cci_halt_req;

typedef union{
    _cci_cci_halt_req bitfields,bits;
    unsigned int u32All;

} CCI_CCI_HALT_REQ;

typedef struct{
    unsigned  I2C_M0_CLK_DISABLE : 1; /* 0:0 */
    unsigned  I2C_M1_CLK_DISABLE : 1; /* 1:1 */
    unsigned  GPIO_0_CLK_DISABLE : 1; /* 2:2 */
    unsigned  GPIO_1_CLK_DISABLE : 1; /* 3:3 */
    unsigned  GPIO_2_CLK_DISABLE : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _cci_cci_clk_disable;

typedef union{
    _cci_cci_clk_disable bitfields,bits;
    unsigned int u32All;

} CCI_CCI_CLK_DISABLE;

typedef struct{
    unsigned  HW_TLOW : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  HW_THIGH : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _cci_cci_i2c_m0_scl_ctl;

typedef union{
    _cci_cci_i2c_m0_scl_ctl bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_SCL_CTL;

typedef struct{
    unsigned  HW_TSU_STA : 8; /* 7:0 */
    unsigned  UNUSED0 : 8; /* 15:8 */
    unsigned  HW_TSU_STO : 8; /* 23:16 */
    unsigned  UNUSED1 : 8; /* 31:24 */
} _cci_cci_i2c_m0_sda_ctl_0;

typedef union{
    _cci_cci_i2c_m0_sda_ctl_0 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_SDA_CTL_0;

typedef struct{
    unsigned  HW_THD_STA : 8; /* 7:0 */
    unsigned  UNUSED0 : 8; /* 15:8 */
    unsigned  HW_THD_DAT : 8; /* 23:16 */
    unsigned  UNUSED1 : 8; /* 31:24 */
} _cci_cci_i2c_m0_sda_ctl_1;

typedef union{
    _cci_cci_i2c_m0_sda_ctl_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_SDA_CTL_1;

typedef struct{
    unsigned  HW_TBUF : 12; /* 11:0 */
    unsigned  UNUSED0 : 20; /* 31:12 */
} _cci_cci_i2c_m0_sda_ctl_2;

typedef union{
    _cci_cci_i2c_m0_sda_ctl_2 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_SDA_CTL_2;

typedef struct{
    unsigned  HW_TSP : 2; /* 1:0 */
    unsigned  UNUSED0 : 2; /* 3:2 */
    unsigned  HW_TRDHLD : 3; /* 6:4 */
    unsigned  UNUSED1 : 1; /* 7:7 */
    unsigned  HW_SCL_STRETCH_EN : 1; /* 8:8 */
    unsigned  HW_DBG_I2C_WR_LOOPBACK_EN : 1; /* 9:9 */
    unsigned  UNUSED2 : 22; /* 31:10 */
} _cci_cci_i2c_m0_misc_ctl;

typedef union{
    _cci_cci_i2c_m0_misc_ctl bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_MISC_CTL;

typedef struct{
    unsigned  BIT_FSM_STATE : 11; /* 10:0 */
    unsigned  UNUSED0 : 1; /* 11:11 */
    unsigned  SDA_OUT : 1; /* 12:12 */
    unsigned  SCL_OUT : 1; /* 13:13 */
    unsigned  SDA_IN : 1; /* 14:14 */
    unsigned  SCL_IN : 1; /* 15:15 */
    unsigned  WORD_FSM_STATE : 7; /* 22:16 */
    unsigned  ACK_FSM_STATE : 3; /* 25:23 */
    unsigned  UNUSED1 : 2; /* 27:26 */
    unsigned  CMD_FSM_STATE : 4; /* 31:28 */
} _cci_cci_i2c_m0_status;

typedef union{
    _cci_cci_i2c_m0_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_STATUS;

typedef struct{
    unsigned  READ_DATA : 32; /* 31:0 */
} _cci_cci_i2c_m0_read_data;

typedef union{
    _cci_cci_i2c_m0_read_data bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_READ_DATA;

typedef struct{
    unsigned  READ_BUF_LEVEL : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_i2c_m0_read_buf_level;

typedef union{
    _cci_cci_i2c_m0_read_buf_level bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_READ_BUF_LEVEL;

typedef struct{
    unsigned  THRESHOLD : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_i2c_m0_rd_threshold;

typedef union{
    _cci_cci_i2c_m0_rd_threshold bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_RD_THRESHOLD;

typedef struct{
    unsigned  HW_TLOW : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  HW_THIGH : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _cci_cci_i2c_m1_scl_ctl;

typedef union{
    _cci_cci_i2c_m1_scl_ctl bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_SCL_CTL;

typedef struct{
    unsigned  HW_TSU_STA : 8; /* 7:0 */
    unsigned  UNUSED0 : 8; /* 15:8 */
    unsigned  HW_TSU_STO : 8; /* 23:16 */
    unsigned  UNUSED1 : 8; /* 31:24 */
} _cci_cci_i2c_m1_sda_ctl_0;

typedef union{
    _cci_cci_i2c_m1_sda_ctl_0 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_SDA_CTL_0;

typedef struct{
    unsigned  HW_THD_STA : 8; /* 7:0 */
    unsigned  UNUSED0 : 8; /* 15:8 */
    unsigned  HW_THD_DAT : 8; /* 23:16 */
    unsigned  UNUSED1 : 8; /* 31:24 */
} _cci_cci_i2c_m1_sda_ctl_1;

typedef union{
    _cci_cci_i2c_m1_sda_ctl_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_SDA_CTL_1;

typedef struct{
    unsigned  HW_TBUF : 12; /* 11:0 */
    unsigned  UNUSED0 : 20; /* 31:12 */
} _cci_cci_i2c_m1_sda_ctl_2;

typedef union{
    _cci_cci_i2c_m1_sda_ctl_2 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_SDA_CTL_2;

typedef struct{
    unsigned  HW_TSP : 2; /* 1:0 */
    unsigned  UNUSED0 : 2; /* 3:2 */
    unsigned  HW_TRDHLD : 3; /* 6:4 */
    unsigned  UNUSED1 : 1; /* 7:7 */
    unsigned  HW_SCL_STRETCH_EN : 1; /* 8:8 */
    unsigned  HW_DBG_I2C_WR_LOOPBACK_EN : 1; /* 9:9 */
    unsigned  UNUSED2 : 22; /* 31:10 */
} _cci_cci_i2c_m1_misc_ctl;

typedef union{
    _cci_cci_i2c_m1_misc_ctl bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_MISC_CTL;

typedef struct{
    unsigned  BIT_FSM_STATE : 11; /* 10:0 */
    unsigned  UNUSED0 : 1; /* 11:11 */
    unsigned  SDA_OUT : 1; /* 12:12 */
    unsigned  SCL_OUT : 1; /* 13:13 */
    unsigned  SDA_IN : 1; /* 14:14 */
    unsigned  SCL_IN : 1; /* 15:15 */
    unsigned  WORD_FSM_STATE : 7; /* 22:16 */
    unsigned  ACK_FSM_STATE : 3; /* 25:23 */
    unsigned  UNUSED1 : 2; /* 27:26 */
    unsigned  CMD_FSM_STATE : 4; /* 31:28 */
} _cci_cci_i2c_m1_status;

typedef union{
    _cci_cci_i2c_m1_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_STATUS;

typedef struct{
    unsigned  READ_DATA : 32; /* 31:0 */
} _cci_cci_i2c_m1_read_data;

typedef union{
    _cci_cci_i2c_m1_read_data bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_READ_DATA;

typedef struct{
    unsigned  READ_BUF_LEVEL : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_i2c_m1_read_buf_level;

typedef union{
    _cci_cci_i2c_m1_read_buf_level bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_READ_BUF_LEVEL;

typedef struct{
    unsigned  THRESHOLD : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_i2c_m1_rd_threshold;

typedef union{
    _cci_cci_i2c_m1_rd_threshold bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_RD_THRESHOLD;

typedef struct{
    unsigned  EXEC_WORD_CNT : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cci_cci_i2c_m0_q0_exec_word_cnt;

typedef union{
    _cci_cci_i2c_m0_q0_exec_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q0_EXEC_WORD_CNT;

typedef struct{
    unsigned  CUR_WORD_CNT : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cci_cci_i2c_m0_q0_cur_word_cnt;

typedef union{
    _cci_cci_i2c_m0_q0_cur_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q0_CUR_WORD_CNT;

typedef struct{
    unsigned  CUR_CMD : 32; /* 31:0 */
} _cci_cci_i2c_m0_q0_cur_cmd;

typedef union{
    _cci_cci_i2c_m0_q0_cur_cmd bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q0_CUR_CMD;

typedef struct{
    unsigned  LINE_CNT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FRAME_CNT : 8; /* 23:16 */
    unsigned  CID : 4; /* 27:24 */
    unsigned  REPORT_ID : 4; /* 31:28 */
} _cci_cci_i2c_m0_q0_report_status;

typedef union{
    _cci_cci_i2c_m0_q0_report_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q0_REPORT_STATUS;

typedef struct{
    unsigned  LOAD_DATA : 32; /* 31:0 */
} _cci_cci_i2c_m0_q0_load_data;

typedef union{
    _cci_cci_i2c_m0_q0_load_data bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q0_LOAD_DATA;

typedef struct{
    unsigned  SLAVE_ID : 7; /* 6:0 */
    unsigned  UNUSED0 : 5; /* 11:7 */
    unsigned  RETRY_CNT : 2; /* 13:12 */
    unsigned  CSI_SENSOR_SYNC_ID : 2; /* 15:14 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _cci_cci_i2c_m0_q0_debug_info;

typedef union{
    _cci_cci_i2c_m0_q0_debug_info bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q0_DEBUG_INFO;

typedef struct{
    unsigned  CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_i2c_m0_q0_report_status_1;

typedef union{
    _cci_cci_i2c_m0_q0_report_status_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q0_REPORT_STATUS_1;

typedef struct{
    unsigned  EXEC_WORD_CNT : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _cci_cci_i2c_m0_q1_exec_word_cnt;

typedef union{
    _cci_cci_i2c_m0_q1_exec_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q1_EXEC_WORD_CNT;

typedef struct{
    unsigned  CUR_WORD_CNT : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _cci_cci_i2c_m0_q1_cur_word_cnt;

typedef union{
    _cci_cci_i2c_m0_q1_cur_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q1_CUR_WORD_CNT;

typedef struct{
    unsigned  CUR_CMD : 32; /* 31:0 */
} _cci_cci_i2c_m0_q1_cur_cmd;

typedef union{
    _cci_cci_i2c_m0_q1_cur_cmd bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q1_CUR_CMD;

typedef struct{
    unsigned  LINE_CNT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FRAME_CNT : 8; /* 23:16 */
    unsigned  CID : 4; /* 27:24 */
    unsigned  REPORT_ID : 4; /* 31:28 */
} _cci_cci_i2c_m0_q1_report_status;

typedef union{
    _cci_cci_i2c_m0_q1_report_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q1_REPORT_STATUS;

typedef struct{
    unsigned  LOAD_DATA : 32; /* 31:0 */
} _cci_cci_i2c_m0_q1_load_data;

typedef union{
    _cci_cci_i2c_m0_q1_load_data bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q1_LOAD_DATA;

typedef struct{
    unsigned  SLAVE_ID : 7; /* 6:0 */
    unsigned  UNUSED0 : 5; /* 11:7 */
    unsigned  RETRY_CNT : 2; /* 13:12 */
    unsigned  CSI_SENSOR_SYNC_ID : 2; /* 15:14 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _cci_cci_i2c_m0_q1_debug_info;

typedef union{
    _cci_cci_i2c_m0_q1_debug_info bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q1_DEBUG_INFO;

typedef struct{
    unsigned  CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_i2c_m0_q1_report_status_1;

typedef union{
    _cci_cci_i2c_m0_q1_report_status_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M0_Q1_REPORT_STATUS_1;

typedef struct{
    unsigned  EXEC_WORD_CNT : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cci_cci_i2c_m1_q0_exec_word_cnt;

typedef union{
    _cci_cci_i2c_m1_q0_exec_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q0_EXEC_WORD_CNT;

typedef struct{
    unsigned  CUR_WORD_CNT : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cci_cci_i2c_m1_q0_cur_word_cnt;

typedef union{
    _cci_cci_i2c_m1_q0_cur_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q0_CUR_WORD_CNT;

typedef struct{
    unsigned  CUR_CMD : 32; /* 31:0 */
} _cci_cci_i2c_m1_q0_cur_cmd;

typedef union{
    _cci_cci_i2c_m1_q0_cur_cmd bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q0_CUR_CMD;

typedef struct{
    unsigned  LINE_CNT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FRAME_CNT : 8; /* 23:16 */
    unsigned  CID : 4; /* 27:24 */
    unsigned  REPORT_ID : 4; /* 31:28 */
} _cci_cci_i2c_m1_q0_report_status;

typedef union{
    _cci_cci_i2c_m1_q0_report_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q0_REPORT_STATUS;

typedef struct{
    unsigned  LOAD_DATA : 32; /* 31:0 */
} _cci_cci_i2c_m1_q0_load_data;

typedef union{
    _cci_cci_i2c_m1_q0_load_data bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q0_LOAD_DATA;

typedef struct{
    unsigned  SLAVE_ID : 7; /* 6:0 */
    unsigned  UNUSED0 : 5; /* 11:7 */
    unsigned  RETRY_CNT : 2; /* 13:12 */
    unsigned  CSI_SENSOR_SYNC_ID : 2; /* 15:14 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _cci_cci_i2c_m1_q0_debug_info;

typedef union{
    _cci_cci_i2c_m1_q0_debug_info bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q0_DEBUG_INFO;

typedef struct{
    unsigned  CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_i2c_m1_q0_report_status_1;

typedef union{
    _cci_cci_i2c_m1_q0_report_status_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q0_REPORT_STATUS_1;

typedef struct{
    unsigned  EXEC_WORD_CNT : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _cci_cci_i2c_m1_q1_exec_word_cnt;

typedef union{
    _cci_cci_i2c_m1_q1_exec_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q1_EXEC_WORD_CNT;

typedef struct{
    unsigned  CUR_WORD_CNT : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _cci_cci_i2c_m1_q1_cur_word_cnt;

typedef union{
    _cci_cci_i2c_m1_q1_cur_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q1_CUR_WORD_CNT;

typedef struct{
    unsigned  CUR_CMD : 32; /* 31:0 */
} _cci_cci_i2c_m1_q1_cur_cmd;

typedef union{
    _cci_cci_i2c_m1_q1_cur_cmd bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q1_CUR_CMD;

typedef struct{
    unsigned  LINE_CNT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FRAME_CNT : 8; /* 23:16 */
    unsigned  CID : 4; /* 27:24 */
    unsigned  REPORT_ID : 4; /* 31:28 */
} _cci_cci_i2c_m1_q1_report_status;

typedef union{
    _cci_cci_i2c_m1_q1_report_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q1_REPORT_STATUS;

typedef struct{
    unsigned  LOAD_DATA : 32; /* 31:0 */
} _cci_cci_i2c_m1_q1_load_data;

typedef union{
    _cci_cci_i2c_m1_q1_load_data bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q1_LOAD_DATA;

typedef struct{
    unsigned  SLAVE_ID : 7; /* 6:0 */
    unsigned  UNUSED0 : 5; /* 11:7 */
    unsigned  RETRY_CNT : 2; /* 13:12 */
    unsigned  CSI_SENSOR_SYNC_ID : 2; /* 15:14 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _cci_cci_i2c_m1_q1_debug_info;

typedef union{
    _cci_cci_i2c_m1_q1_debug_info bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q1_DEBUG_INFO;

typedef struct{
    unsigned  CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_i2c_m1_q1_report_status_1;

typedef union{
    _cci_cci_i2c_m1_q1_report_status_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_I2C_M1_Q1_REPORT_STATUS_1;

typedef struct{
    unsigned  EXEC_WORD_CNT : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _cci_cci_gpio_q0_exec_word_cnt;

typedef union{
    _cci_cci_gpio_q0_exec_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q0_EXEC_WORD_CNT;

typedef struct{
    unsigned  CUR_WORD_CNT : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _cci_cci_gpio_q0_cur_word_cnt;

typedef union{
    _cci_cci_gpio_q0_cur_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q0_CUR_WORD_CNT;

typedef struct{
    unsigned  CUR_CMD : 32; /* 31:0 */
} _cci_cci_gpio_q0_cur_cmd;

typedef union{
    _cci_cci_gpio_q0_cur_cmd bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q0_CUR_CMD;

typedef struct{
    unsigned  LINE_CNT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FRAME_CNT : 8; /* 23:16 */
    unsigned  CID : 4; /* 27:24 */
    unsigned  REPORT_ID : 4; /* 31:28 */
} _cci_cci_gpio_q0_report_status;

typedef union{
    _cci_cci_gpio_q0_report_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q0_REPORT_STATUS;

typedef struct{
    unsigned  LOAD_DATA : 32; /* 31:0 */
} _cci_cci_gpio_q0_load_data;

typedef union{
    _cci_cci_gpio_q0_load_data bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q0_LOAD_DATA;

typedef struct{
    unsigned  CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_gpio_q0_report_status_1;

typedef union{
    _cci_cci_gpio_q0_report_status_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q0_REPORT_STATUS_1;

typedef struct{
    unsigned  EXEC_WORD_CNT : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _cci_cci_gpio_q1_exec_word_cnt;

typedef union{
    _cci_cci_gpio_q1_exec_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q1_EXEC_WORD_CNT;

typedef struct{
    unsigned  CUR_WORD_CNT : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _cci_cci_gpio_q1_cur_word_cnt;

typedef union{
    _cci_cci_gpio_q1_cur_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q1_CUR_WORD_CNT;

typedef struct{
    unsigned  CUR_CMD : 32; /* 31:0 */
} _cci_cci_gpio_q1_cur_cmd;

typedef union{
    _cci_cci_gpio_q1_cur_cmd bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q1_CUR_CMD;

typedef struct{
    unsigned  LINE_CNT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FRAME_CNT : 8; /* 23:16 */
    unsigned  CID : 4; /* 27:24 */
    unsigned  REPORT_ID : 4; /* 31:28 */
} _cci_cci_gpio_q1_report_status;

typedef union{
    _cci_cci_gpio_q1_report_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q1_REPORT_STATUS;

typedef struct{
    unsigned  LOAD_DATA : 32; /* 31:0 */
} _cci_cci_gpio_q1_load_data;

typedef union{
    _cci_cci_gpio_q1_load_data bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q1_LOAD_DATA;

typedef struct{
    unsigned  CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_gpio_q1_report_status_1;

typedef union{
    _cci_cci_gpio_q1_report_status_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q1_REPORT_STATUS_1;

typedef struct{
    unsigned  EXEC_WORD_CNT : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _cci_cci_gpio_q2_exec_word_cnt;

typedef union{
    _cci_cci_gpio_q2_exec_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q2_EXEC_WORD_CNT;

typedef struct{
    unsigned  CUR_WORD_CNT : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _cci_cci_gpio_q2_cur_word_cnt;

typedef union{
    _cci_cci_gpio_q2_cur_word_cnt bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q2_CUR_WORD_CNT;

typedef struct{
    unsigned  CUR_CMD : 32; /* 31:0 */
} _cci_cci_gpio_q2_cur_cmd;

typedef union{
    _cci_cci_gpio_q2_cur_cmd bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q2_CUR_CMD;

typedef struct{
    unsigned  LINE_CNT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FRAME_CNT : 8; /* 23:16 */
    unsigned  CID : 4; /* 27:24 */
    unsigned  REPORT_ID : 4; /* 31:28 */
} _cci_cci_gpio_q2_report_status;

typedef union{
    _cci_cci_gpio_q2_report_status bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q2_REPORT_STATUS;

typedef struct{
    unsigned  LOAD_DATA : 32; /* 31:0 */
} _cci_cci_gpio_q2_load_data;

typedef union{
    _cci_cci_gpio_q2_load_data bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q2_LOAD_DATA;

typedef struct{
    unsigned  CID : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _cci_cci_gpio_q2_report_status_1;

typedef union{
    _cci_cci_gpio_q2_report_status_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_GPIO_Q2_REPORT_STATUS_1;

typedef struct{
    unsigned  GLOBAL_CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _cci_cci_irq_global_clear_cmd;

typedef union{
    _cci_cci_irq_global_clear_cmd bitfields,bits;
    unsigned int u32All;

} CCI_CCI_IRQ_GLOBAL_CLEAR_CMD;

typedef struct{
    unsigned  I2C_M0_RD_DONE : 1; /* 0:0 */
    unsigned  I2C_M0_RD_UNDERFLOW : 1; /* 1:1 */
    unsigned  I2C_M0_RD_OVERFLOW : 1; /* 2:2 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  I2C_M0_Q0_REPORT : 1; /* 4:4 */
    unsigned  I2C_M0_Q0_UNDERFLOW : 1; /* 5:5 */
    unsigned  I2C_M0_Q0_OVERFLOW : 1; /* 6:6 */
    unsigned  I2C_M0_Q0_CMD_ERR : 1; /* 7:7 */
    unsigned  I2C_M0_Q1_REPORT : 1; /* 8:8 */
    unsigned  I2C_M0_Q1_UNDERFLOW : 1; /* 9:9 */
    unsigned  I2C_M0_Q1_OVERFLOW : 1; /* 10:10 */
    unsigned  I2C_M0_Q1_CMD_ERR : 1; /* 11:11 */
    unsigned  I2C_M1_RD_DONE : 1; /* 12:12 */
    unsigned  I2C_M1_RD_UNDERFLOW : 1; /* 13:13 */
    unsigned  I2C_M1_RD_OVERFLOW : 1; /* 14:14 */
    unsigned  UNUSED1 : 1; /* 15:15 */
    unsigned  I2C_M1_Q0_REPORT : 1; /* 16:16 */
    unsigned  I2C_M1_Q0_UNDERFLOW : 1; /* 17:17 */
    unsigned  I2C_M1_Q0_OVERFLOW : 1; /* 18:18 */
    unsigned  I2C_M1_Q0_CMD_ERR : 1; /* 19:19 */
    unsigned  I2C_M1_Q1_REPORT : 1; /* 20:20 */
    unsigned  I2C_M1_Q1_UNDERFLOW : 1; /* 21:21 */
    unsigned  I2C_M1_Q1_OVERFLOW : 1; /* 22:22 */
    unsigned  I2C_M1_Q1_CMD_ERR : 1; /* 23:23 */
    unsigned  RST_DONE_ACK : 1; /* 24:24 */
    unsigned  I2C_M0_Q0Q1_HALT_ACK : 1; /* 25:25 */
    unsigned  I2C_M1_Q0Q1_HALT_ACK : 1; /* 26:26 */
    unsigned  I2C_M0_Q0_NACK_ERR : 1; /* 27:27 */
    unsigned  I2C_M0_Q1_NACK_ERR : 1; /* 28:28 */
    unsigned  I2C_M1_Q0_NACK_ERR : 1; /* 29:29 */
    unsigned  I2C_M1_Q1_NACK_ERR : 1; /* 30:30 */
    unsigned  UNUSED2 : 1; /* 31:31 */
} _cci_cci_irq_mask_0;

typedef union{
    _cci_cci_irq_mask_0 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_IRQ_MASK_0;

typedef struct{
    unsigned  I2C_M0_RD_DONE : 1; /* 0:0 */
    unsigned  I2C_M0_RD_UNDERFLOW : 1; /* 1:1 */
    unsigned  I2C_M0_RD_OVERFLOW : 1; /* 2:2 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  I2C_M0_Q0_REPORT : 1; /* 4:4 */
    unsigned  I2C_M0_Q0_UNDERFLOW : 1; /* 5:5 */
    unsigned  I2C_M0_Q0_OVERFLOW : 1; /* 6:6 */
    unsigned  I2C_M0_Q0_CMD_ERR : 1; /* 7:7 */
    unsigned  I2C_M0_Q1_REPORT : 1; /* 8:8 */
    unsigned  I2C_M0_Q1_UNDERFLOW : 1; /* 9:9 */
    unsigned  I2C_M0_Q1_OVERFLOW : 1; /* 10:10 */
    unsigned  I2C_M0_Q1_CMD_ERR : 1; /* 11:11 */
    unsigned  I2C_M1_RD_DONE : 1; /* 12:12 */
    unsigned  I2C_M1_RD_UNDERFLOW : 1; /* 13:13 */
    unsigned  I2C_M1_RD_OVERFLOW : 1; /* 14:14 */
    unsigned  UNUSED1 : 1; /* 15:15 */
    unsigned  I2C_M1_Q0_REPORT : 1; /* 16:16 */
    unsigned  I2C_M1_Q0_UNDERFLOW : 1; /* 17:17 */
    unsigned  I2C_M1_Q0_OVERFLOW : 1; /* 18:18 */
    unsigned  I2C_M1_Q0_CMD_ERR : 1; /* 19:19 */
    unsigned  I2C_M1_Q1_REPORT : 1; /* 20:20 */
    unsigned  I2C_M1_Q1_UNDERFLOW : 1; /* 21:21 */
    unsigned  I2C_M1_Q1_OVERFLOW : 1; /* 22:22 */
    unsigned  I2C_M1_Q1_CMD_ERR : 1; /* 23:23 */
    unsigned  RST_DONE_ACK : 1; /* 24:24 */
    unsigned  I2C_M0_Q0Q1_HALT_ACK : 1; /* 25:25 */
    unsigned  I2C_M1_Q0Q1_HALT_ACK : 1; /* 26:26 */
    unsigned  I2C_M0_Q0_NACK_ERR : 1; /* 27:27 */
    unsigned  I2C_M0_Q1_NACK_ERR : 1; /* 28:28 */
    unsigned  I2C_M1_Q0_NACK_ERR : 1; /* 29:29 */
    unsigned  I2C_M1_Q1_NACK_ERR : 1; /* 30:30 */
    unsigned  UNUSED2 : 1; /* 31:31 */
} _cci_cci_irq_clear_0;

typedef union{
    _cci_cci_irq_clear_0 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_IRQ_CLEAR_0;

typedef struct{
    unsigned  I2C_M0_RD_DONE : 1; /* 0:0 */
    unsigned  I2C_M0_RD_UNDERFLOW : 1; /* 1:1 */
    unsigned  I2C_M0_RD_OVERFLOW : 1; /* 2:2 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  I2C_M0_Q0_REPORT : 1; /* 4:4 */
    unsigned  I2C_M0_Q0_UNDERFLOW : 1; /* 5:5 */
    unsigned  I2C_M0_Q0_OVERFLOW : 1; /* 6:6 */
    unsigned  I2C_M0_Q0_CMD_ERR : 1; /* 7:7 */
    unsigned  I2C_M0_Q1_REPORT : 1; /* 8:8 */
    unsigned  I2C_M0_Q1_UNDERFLOW : 1; /* 9:9 */
    unsigned  I2C_M0_Q1_OVERFLOW : 1; /* 10:10 */
    unsigned  I2C_M0_Q1_CMD_ERR : 1; /* 11:11 */
    unsigned  I2C_M1_RD_DONE : 1; /* 12:12 */
    unsigned  I2C_M1_RD_UNDERFLOW : 1; /* 13:13 */
    unsigned  I2C_M1_RD_OVERFLOW : 1; /* 14:14 */
    unsigned  UNUSED1 : 1; /* 15:15 */
    unsigned  I2C_M1_Q0_REPORT : 1; /* 16:16 */
    unsigned  I2C_M1_Q0_UNDERFLOW : 1; /* 17:17 */
    unsigned  I2C_M1_Q0_OVERFLOW : 1; /* 18:18 */
    unsigned  I2C_M1_Q0_CMD_ERR : 1; /* 19:19 */
    unsigned  I2C_M1_Q1_REPORT : 1; /* 20:20 */
    unsigned  I2C_M1_Q1_UNDERFLOW : 1; /* 21:21 */
    unsigned  I2C_M1_Q1_OVERFLOW : 1; /* 22:22 */
    unsigned  I2C_M1_Q1_CMD_ERR : 1; /* 23:23 */
    unsigned  RST_DONE_ACK : 1; /* 24:24 */
    unsigned  I2C_M0_Q0Q1_HALT_ACK : 1; /* 25:25 */
    unsigned  I2C_M1_Q0Q1_HALT_ACK : 1; /* 26:26 */
    unsigned  I2C_M0_Q0_NACK_ERR : 1; /* 27:27 */
    unsigned  I2C_M0_Q1_NACK_ERR : 1; /* 28:28 */
    unsigned  I2C_M1_Q0_NACK_ERR : 1; /* 29:29 */
    unsigned  I2C_M1_Q1_NACK_ERR : 1; /* 30:30 */
    unsigned  UNUSED2 : 1; /* 31:31 */
} _cci_cci_irq_status_0;

typedef union{
    _cci_cci_irq_status_0 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_IRQ_STATUS_0;

typedef struct{
    unsigned  GPIO_Q0_REPORT : 1; /* 0:0 */
    unsigned  GPIO_Q0_UNDERFLOW : 1; /* 1:1 */
    unsigned  GPIO_Q0_OVERFLOW : 1; /* 2:2 */
    unsigned  GPIO_Q0_CMD_ERR : 1; /* 3:3 */
    unsigned  GPIO_Q1_REPORT : 1; /* 4:4 */
    unsigned  GPIO_Q1_UNDERFLOW : 1; /* 5:5 */
    unsigned  GPIO_Q1_OVERFLOW : 1; /* 6:6 */
    unsigned  GPIO_Q1_CMD_ERR : 1; /* 7:7 */
    unsigned  GPIO_Q2_REPORT : 1; /* 8:8 */
    unsigned  GPIO_Q2_UNDERFLOW : 1; /* 9:9 */
    unsigned  GPIO_Q2_OVERFLOW : 1; /* 10:10 */
    unsigned  GPIO_Q2_CMD_ERR : 1; /* 11:11 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  I2C_M0_RD_THRESHOLD : 1; /* 16:16 */
    unsigned  I2C_M0_RD_PAUSE : 1; /* 17:17 */
    unsigned  I2C_M0_Q0_CMD_THRESHOLD : 1; /* 18:18 */
    unsigned  I2C_M0_Q1_CMD_THRESHOLD : 1; /* 19:19 */
    unsigned  I2C_M1_RD_THRESHOLD : 1; /* 20:20 */
    unsigned  I2C_M1_RD_PAUSE : 1; /* 21:21 */
    unsigned  I2C_M1_Q0_CMD_THRESHOLD : 1; /* 22:22 */
    unsigned  I2C_M1_Q1_CMD_THRESHOLD : 1; /* 23:23 */
    unsigned  UNUSED1 : 8; /* 31:24 */
} _cci_cci_irq_mask_1;

typedef union{
    _cci_cci_irq_mask_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_IRQ_MASK_1;

typedef struct{
    unsigned  GPIO_Q0_REPORT : 1; /* 0:0 */
    unsigned  GPIO_Q0_UNDERFLOW : 1; /* 1:1 */
    unsigned  GPIO_Q0_OVERFLOW : 1; /* 2:2 */
    unsigned  GPIO_Q0_CMD_ERR : 1; /* 3:3 */
    unsigned  GPIO_Q1_REPORT : 1; /* 4:4 */
    unsigned  GPIO_Q1_UNDERFLOW : 1; /* 5:5 */
    unsigned  GPIO_Q1_OVERFLOW : 1; /* 6:6 */
    unsigned  GPIO_Q1_CMD_ERR : 1; /* 7:7 */
    unsigned  GPIO_Q2_REPORT : 1; /* 8:8 */
    unsigned  GPIO_Q2_UNDERFLOW : 1; /* 9:9 */
    unsigned  GPIO_Q2_OVERFLOW : 1; /* 10:10 */
    unsigned  GPIO_Q2_CMD_ERR : 1; /* 11:11 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  I2C_M0_RD_THRESHOLD : 1; /* 16:16 */
    unsigned  I2C_M0_RD_PAUSE : 1; /* 17:17 */
    unsigned  I2C_M0_Q0_CMD_THRESHOLD : 1; /* 18:18 */
    unsigned  I2C_M0_Q1_CMD_THRESHOLD : 1; /* 19:19 */
    unsigned  I2C_M1_RD_THRESHOLD : 1; /* 20:20 */
    unsigned  I2C_M1_RD_PAUSE : 1; /* 21:21 */
    unsigned  I2C_M1_Q0_CMD_THRESHOLD : 1; /* 22:22 */
    unsigned  I2C_M1_Q1_CMD_THRESHOLD : 1; /* 23:23 */
    unsigned  UNUSED1 : 8; /* 31:24 */
} _cci_cci_irq_clear_1;

typedef union{
    _cci_cci_irq_clear_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_IRQ_CLEAR_1;

typedef struct{
    unsigned  GPIO_Q0_REPORT : 1; /* 0:0 */
    unsigned  GPIO_Q0_UNDERFLOW : 1; /* 1:1 */
    unsigned  GPIO_Q0_OVERFLOW : 1; /* 2:2 */
    unsigned  GPIO_Q0_CMD_ERR : 1; /* 3:3 */
    unsigned  GPIO_Q1_REPORT : 1; /* 4:4 */
    unsigned  GPIO_Q1_UNDERFLOW : 1; /* 5:5 */
    unsigned  GPIO_Q1_OVERFLOW : 1; /* 6:6 */
    unsigned  GPIO_Q1_CMD_ERR : 1; /* 7:7 */
    unsigned  GPIO_Q2_REPORT : 1; /* 8:8 */
    unsigned  GPIO_Q2_UNDERFLOW : 1; /* 9:9 */
    unsigned  GPIO_Q2_OVERFLOW : 1; /* 10:10 */
    unsigned  GPIO_Q2_CMD_ERR : 1; /* 11:11 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  I2C_M0_RD_THRESHOLD : 1; /* 16:16 */
    unsigned  I2C_M0_RD_PAUSE : 1; /* 17:17 */
    unsigned  I2C_M0_Q0_CMD_THRESHOLD : 1; /* 18:18 */
    unsigned  I2C_M0_Q1_CMD_THRESHOLD : 1; /* 19:19 */
    unsigned  I2C_M1_RD_THRESHOLD : 1; /* 20:20 */
    unsigned  I2C_M1_RD_PAUSE : 1; /* 21:21 */
    unsigned  I2C_M1_Q0_CMD_THRESHOLD : 1; /* 22:22 */
    unsigned  I2C_M1_Q1_CMD_THRESHOLD : 1; /* 23:23 */
    unsigned  UNUSED1 : 8; /* 31:24 */
} _cci_cci_irq_status_1;

typedef union{
    _cci_cci_irq_status_1 bitfields,bits;
    unsigned int u32All;

} CCI_CCI_IRQ_STATUS_1;

/*----------------------------------------------------------------------
        ENUM Data Structures
----------------------------------------------------------------------*/

typedef enum{
    CCI_CCI_RESET_CMD_STROBED_RST_EN_DISABLE  = 0x0,
    CCI_CCI_RESET_CMD_STROBED_RST_EN_ENABLE  = 0x1
} CCI_CCI_RESET_CMD_STROBED_RST_EN_ENUM;


typedef enum{
    CCI_CCI_RESET_CMD_CCI_CLK_DOMAIN_RST_FUNCTIONAL  = 0x0,
    CCI_CCI_RESET_CMD_CCI_CLK_DOMAIN_RST_RESET  = 0x1
} CCI_CCI_RESET_CMD_CCI_CLK_DOMAIN_RST_ENUM;


typedef enum{
    CCI_CCI_RESET_CMD_AHB_CLK_DOMAIN_RST_FUNCTIONAL  = 0x0,
    CCI_CCI_RESET_CMD_AHB_CLK_DOMAIN_RST_RESET  = 0x1
} CCI_CCI_RESET_CMD_AHB_CLK_DOMAIN_RST_ENUM;


typedef enum{
    CCI_CCI_TESTBUS_SEL_TESTBUS_EN_DISABLE  = 0x0,
    CCI_CCI_TESTBUS_SEL_TESTBUS_EN_ENABLE  = 0x1
} CCI_CCI_TESTBUS_SEL_TESTBUS_EN_ENUM;


typedef enum{
    CCI_CCI_TESTBUS_SEL_DOMAIN_SEL_CC_AHB_CLK  = 0x0,
    CCI_CCI_TESTBUS_SEL_DOMAIN_SEL_CC_CCI_CLK  = 0x1
} CCI_CCI_TESTBUS_SEL_DOMAIN_SEL_ENUM;


typedef enum{
    CCI_CCI_I2C_M0_MISC_CTL_HW_TSP_NO_FILTERING  = 0x0,
    CCI_CCI_I2C_M0_MISC_CTL_HW_TSP_ONE_CCI_CLOCK  = 0x1,
    CCI_CCI_I2C_M0_MISC_CTL_HW_TSP_TWO_CCI_CLOCKS  = 0x2,
    CCI_CCI_I2C_M0_MISC_CTL_HW_TSP_THREE_CCI_CLOCKS  = 0x3
} CCI_CCI_I2C_M0_MISC_CTL_HW_TSP_ENUM;


typedef enum{
    CCI_CCI_I2C_M0_MISC_CTL_HW_SCL_STRETCH_EN_DISABLE  = 0x0,
    CCI_CCI_I2C_M0_MISC_CTL_HW_SCL_STRETCH_EN_ENABLE  = 0x1
} CCI_CCI_I2C_M0_MISC_CTL_HW_SCL_STRETCH_EN_ENUM;


typedef enum{
    CCI_CCI_I2C_M0_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_DISABLE  = 0x0,
    CCI_CCI_I2C_M0_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_ENABLE  = 0x1
} CCI_CCI_I2C_M0_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_ENUM;


typedef enum{
    CCI_CCI_I2C_M1_MISC_CTL_HW_TSP_NO_FILTERING  = 0x0,
    CCI_CCI_I2C_M1_MISC_CTL_HW_TSP_ONE_CCI_CLOCK  = 0x1,
    CCI_CCI_I2C_M1_MISC_CTL_HW_TSP_TWO_CCI_CLOCKS  = 0x2,
    CCI_CCI_I2C_M1_MISC_CTL_HW_TSP_THREE_CCI_CLOCKS  = 0x3
} CCI_CCI_I2C_M1_MISC_CTL_HW_TSP_ENUM;


typedef enum{
    CCI_CCI_I2C_M1_MISC_CTL_HW_SCL_STRETCH_EN_DISABLE  = 0x0,
    CCI_CCI_I2C_M1_MISC_CTL_HW_SCL_STRETCH_EN_ENABLE  = 0x1
} CCI_CCI_I2C_M1_MISC_CTL_HW_SCL_STRETCH_EN_ENUM;


typedef enum{
    CCI_CCI_I2C_M1_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_DISABLE  = 0x0,
    CCI_CCI_I2C_M1_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_ENABLE  = 0x1
} CCI_CCI_I2C_M1_MISC_CTL_HW_DBG_I2C_WR_LOOPBACK_EN_ENUM;

#endif // TITAN170_CCI_H
